Struct esp32c6::extmem::l1_cache_acs_fail_int_st::R

pub struct R(_);

Register L1_CACHE_ACS_FAIL_INT_ST reader

Implementations

impl R

pub fn l1_icache0_fail_int_st(&self) -> L1_ICACHE0_FAIL_INT_ST_R

Bit 0 - The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache.

pub fn l1_icache1_fail_int_st(&self) -> L1_ICACHE1_FAIL_INT_ST_R

Bit 1 - The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache.

pub fn l1_icache2_fail_int_st(&self) -> L1_ICACHE2_FAIL_INT_ST_R

Bit 2 - Reserved

pub fn l1_icache3_fail_int_st(&self) -> L1_ICACHE3_FAIL_INT_ST_R

Bit 3 - Reserved

pub fn l1_cache_fail_int_st(&self) -> L1_CACHE_FAIL_INT_ST_R

Bit 4 - The bit indicates the interrupt status of access fail that occurs in L1-DCache due to cpu accesses L1-DCache.

Methods from Deref<Target = R<L1_CACHE_ACS_FAIL_INT_ST_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<L1_CACHE_ACS_FAIL_INT_ST_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<L1_CACHE_ACS_FAIL_INT_ST_SPEC>> for R

fn from(reader: R<L1_CACHE_ACS_FAIL_INT_ST_SPEC>) -> Self

Converts to this type from the input type.