Struct esp32c6::spi0::spi_mem_ctrl1::R

pub struct R(_);

Register SPI_MEM_CTRL1 reader

Implementations

impl R

pub fn spi_mem_clk_mode(&self) -> SPI_MEM_CLK_MODE_R

Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.

pub fn spi_ar_size0_1_support_en(&self) -> SPI_AR_SIZE0_1_SUPPORT_EN_R

Bit 21 - 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.

pub fn spi_aw_size0_1_support_en(&self) -> SPI_AW_SIZE0_1_SUPPORT_EN_R

Bit 22 - 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.

pub fn spi_axi_rdata_back_fast(&self) -> SPI_AXI_RDATA_BACK_FAST_R

Bit 23 - 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available.

pub fn spi_mem_rresp_ecc_err_en(&self) -> SPI_MEM_RRESP_ECC_ERR_EN_R

Bit 24 - 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG.

pub fn spi_mem_ar_splice_en(&self) -> SPI_MEM_AR_SPLICE_EN_R

Bit 25 - Set this bit to enable AXI Read Splice-transfer.

pub fn spi_mem_aw_splice_en(&self) -> SPI_MEM_AW_SPLICE_EN_R

Bit 26 - Set this bit to enable AXI Write Splice-transfer.

pub fn spi_mem_ram0_en(&self) -> SPI_MEM_RAM0_EN_R

Bit 27 - When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be accessed at the same time.

pub fn spi_mem_dual_ram_en(&self) -> SPI_MEM_DUAL_RAM_EN_R

Bit 28 - Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time.

pub fn spi_mem_fast_write_en(&self) -> SPI_MEM_FAST_WRITE_EN_R

Bit 29 - Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2.

Methods from Deref<Target = R<SPI_MEM_CTRL1_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<SPI_MEM_CTRL1_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<SPI_MEM_CTRL1_SPEC>> for R

fn from(reader: R<SPI_MEM_CTRL1_SPEC>) -> Self

Converts to this type from the input type.