1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132

#[doc = "Register `PWM_CLK_CONF` reader"]
pub struct R(crate::R<PWM_CLK_CONF_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<PWM_CLK_CONF_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl From<crate::R<PWM_CLK_CONF_SPEC>> for R {
    #[inline(always)]
    fn from(reader: crate::R<PWM_CLK_CONF_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `PWM_CLK_CONF` writer"]
pub struct W(crate::W<PWM_CLK_CONF_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<PWM_CLK_CONF_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl From<crate::W<PWM_CLK_CONF_SPEC>> for W {
    #[inline(always)]
    fn from(writer: crate::W<PWM_CLK_CONF_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `PWM_DIV_NUM` reader - The integral part of the frequency divider factor of the pwm function clock."]
pub type PWM_DIV_NUM_R = crate::FieldReader;
#[doc = "Field `PWM_DIV_NUM` writer - The integral part of the frequency divider factor of the pwm function clock."]
pub type PWM_DIV_NUM_W<'a, const O: u8> = crate::FieldWriter<'a, PWM_CLK_CONF_SPEC, 8, O>;
#[doc = "Field `PWM_CLKM_SEL` reader - set this field to select clock-source. 0(default): do not select anyone clock, 1: 160MHz, 2: XTAL, 3: FOSC."]
pub type PWM_CLKM_SEL_R = crate::FieldReader;
#[doc = "Field `PWM_CLKM_SEL` writer - set this field to select clock-source. 0(default): do not select anyone clock, 1: 160MHz, 2: XTAL, 3: FOSC."]
pub type PWM_CLKM_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, PWM_CLK_CONF_SPEC, 2, O>;
#[doc = "Field `PWM_CLKM_EN` reader - set this field as 1 to activate pwm clkm."]
pub type PWM_CLKM_EN_R = crate::BitReader;
#[doc = "Field `PWM_CLKM_EN` writer - set this field as 1 to activate pwm clkm."]
pub type PWM_CLKM_EN_W<'a, const O: u8> = crate::BitWriter<'a, PWM_CLK_CONF_SPEC, O>;
impl R {
    #[doc = "Bits 12:19 - The integral part of the frequency divider factor of the pwm function clock."]
    #[inline(always)]
    pub fn pwm_div_num(&self) -> PWM_DIV_NUM_R {
        PWM_DIV_NUM_R::new(((self.bits >> 12) & 0xff) as u8)
    }
    #[doc = "Bits 20:21 - set this field to select clock-source. 0(default): do not select anyone clock, 1: 160MHz, 2: XTAL, 3: FOSC."]
    #[inline(always)]
    pub fn pwm_clkm_sel(&self) -> PWM_CLKM_SEL_R {
        PWM_CLKM_SEL_R::new(((self.bits >> 20) & 3) as u8)
    }
    #[doc = "Bit 22 - set this field as 1 to activate pwm clkm."]
    #[inline(always)]
    pub fn pwm_clkm_en(&self) -> PWM_CLKM_EN_R {
        PWM_CLKM_EN_R::new(((self.bits >> 22) & 1) != 0)
    }
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PWM_CLK_CONF")
            .field(
                "pwm_div_num",
                &format_args!("{}", self.pwm_div_num().bits()),
            )
            .field(
                "pwm_clkm_sel",
                &format_args!("{}", self.pwm_clkm_sel().bits()),
            )
            .field("pwm_clkm_en", &format_args!("{}", self.pwm_clkm_en().bit()))
            .finish()
    }
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<PWM_CLK_CONF_SPEC> {
    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
        self.read().fmt(f)
    }
}
impl W {
    #[doc = "Bits 12:19 - The integral part of the frequency divider factor of the pwm function clock."]
    #[inline(always)]
    #[must_use]
    pub fn pwm_div_num(&mut self) -> PWM_DIV_NUM_W<12> {
        PWM_DIV_NUM_W::new(self)
    }
    #[doc = "Bits 20:21 - set this field to select clock-source. 0(default): do not select anyone clock, 1: 160MHz, 2: XTAL, 3: FOSC."]
    #[inline(always)]
    #[must_use]
    pub fn pwm_clkm_sel(&mut self) -> PWM_CLKM_SEL_W<20> {
        PWM_CLKM_SEL_W::new(self)
    }
    #[doc = "Bit 22 - set this field as 1 to activate pwm clkm."]
    #[inline(always)]
    #[must_use]
    pub fn pwm_clkm_en(&mut self) -> PWM_CLKM_EN_W<22> {
        PWM_CLKM_EN_W::new(self)
    }
    #[doc = "Writes raw bits to the register."]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "PWM_CLK configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pwm_clk_conf](index.html) module"]
pub struct PWM_CLK_CONF_SPEC;
impl crate::RegisterSpec for PWM_CLK_CONF_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [pwm_clk_conf::R](R) reader structure"]
impl crate::Readable for PWM_CLK_CONF_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [pwm_clk_conf::W](W) writer structure"]
impl crate::Writable for PWM_CLK_CONF_SPEC {
    type Writer = W;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets PWM_CLK_CONF to value 0x0040_4000"]
impl crate::Resettable for PWM_CLK_CONF_SPEC {
    const RESET_VALUE: Self::Ux = 0x0040_4000;
}