Module esp32c6::pcr::pll_div_clk_en

source ·
Expand description

SPLL DIV clock-gating configuration register

Structs

  • PLL_DIV_CLK_EN_SPEC
    SPLL DIV clock-gating configuration register
  • R
    Register PLL_DIV_CLK_EN reader
  • W
    Register PLL_DIV_CLK_EN writer

Type Definitions

  • PLL_20M_CLK_EN_R
    Field PLL_20M_CLK_EN reader - This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active.
  • PLL_20M_CLK_EN_W
    Field PLL_20M_CLK_EN writer - This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active.
  • PLL_40M_CLK_EN_R
    Field PLL_40M_CLK_EN reader - This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active.
  • PLL_40M_CLK_EN_W
    Field PLL_40M_CLK_EN writer - This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active.
  • PLL_48M_CLK_EN_R
    Field PLL_48M_CLK_EN reader - This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active.
  • PLL_48M_CLK_EN_W
    Field PLL_48M_CLK_EN writer - This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active.
  • PLL_80M_CLK_EN_R
    Field PLL_80M_CLK_EN reader - This field is used to open 80 MHz clock (div6 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active.
  • PLL_80M_CLK_EN_W
    Field PLL_80M_CLK_EN writer - This field is used to open 80 MHz clock (div6 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active.
  • PLL_120M_CLK_EN_R
    Field PLL_120M_CLK_EN reader - This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active.
  • PLL_120M_CLK_EN_W
    Field PLL_120M_CLK_EN writer - This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active.
  • PLL_160M_CLK_EN_R
    Field PLL_160M_CLK_EN reader - This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active.
  • PLL_160M_CLK_EN_W
    Field PLL_160M_CLK_EN writer - This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active.
  • PLL_240M_CLK_EN_R
    Field PLL_240M_CLK_EN reader - This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active.
  • PLL_240M_CLK_EN_W
    Field PLL_240M_CLK_EN writer - This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active.