Struct esp32c6::spi0::spi_mem_din_num::W
source · pub struct W(_);Expand description
Register SPI_MEM_DIN_NUM writer
Implementations§
source§impl W
impl W
sourcepub fn spi_mem_din0_num(&mut self) -> SPI_MEM_DIN0_NUM_W<'_, 0>
pub fn spi_mem_din0_num(&mut self) -> SPI_MEM_DIN0_NUM_W<'_, 0>
Bits 0:1 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…
sourcepub fn spi_mem_din1_num(&mut self) -> SPI_MEM_DIN1_NUM_W<'_, 2>
pub fn spi_mem_din1_num(&mut self) -> SPI_MEM_DIN1_NUM_W<'_, 2>
Bits 2:3 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…
sourcepub fn spi_mem_din2_num(&mut self) -> SPI_MEM_DIN2_NUM_W<'_, 4>
pub fn spi_mem_din2_num(&mut self) -> SPI_MEM_DIN2_NUM_W<'_, 4>
Bits 4:5 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…
sourcepub fn spi_mem_din3_num(&mut self) -> SPI_MEM_DIN3_NUM_W<'_, 6>
pub fn spi_mem_din3_num(&mut self) -> SPI_MEM_DIN3_NUM_W<'_, 6>
Bits 6:7 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…
sourcepub fn spi_mem_din4_num(&mut self) -> SPI_MEM_DIN4_NUM_W<'_, 8>
pub fn spi_mem_din4_num(&mut self) -> SPI_MEM_DIN4_NUM_W<'_, 8>
Bits 8:9 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…
sourcepub fn spi_mem_din5_num(&mut self) -> SPI_MEM_DIN5_NUM_W<'_, 10>
pub fn spi_mem_din5_num(&mut self) -> SPI_MEM_DIN5_NUM_W<'_, 10>
Bits 10:11 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…
sourcepub fn spi_mem_din6_num(&mut self) -> SPI_MEM_DIN6_NUM_W<'_, 12>
pub fn spi_mem_din6_num(&mut self) -> SPI_MEM_DIN6_NUM_W<'_, 12>
Bits 12:13 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…
sourcepub fn spi_mem_din7_num(&mut self) -> SPI_MEM_DIN7_NUM_W<'_, 14>
pub fn spi_mem_din7_num(&mut self) -> SPI_MEM_DIN7_NUM_W<'_, 14>
Bits 14:15 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…
sourcepub fn spi_mem_dins_num(&mut self) -> SPI_MEM_DINS_NUM_W<'_, 16>
pub fn spi_mem_dins_num(&mut self) -> SPI_MEM_DINS_NUM_W<'_, 16>
Bits 16:17 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…