Struct esp32c6::pcr::sysclk_conf::R

pub struct R(_);

Register SYSCLK_CONF reader

Implementations

impl R

pub fn ls_div_num(&self) -> LS_DIV_NUM_R

Bits 0:7 - clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed clock-source such as XTAL/FOSC.

pub fn hs_div_num(&self) -> HS_DIV_NUM_R

Bits 8:15 - clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL.

pub fn soc_clk_sel(&self) -> SOC_CLK_SEL_R

Bits 16:17 - This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved.

pub fn clk_xtal_freq(&self) -> CLK_XTAL_FREQ_R

Bits 24:30 - This field indicates the frequency(MHz) of XTAL.

Methods from Deref<Target = R<SYSCLK_CONF_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<SYSCLK_CONF_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<SYSCLK_CONF_SPEC>> for R

fn from(reader: R<SYSCLK_CONF_SPEC>) -> Self

Converts to this type from the input type.