Struct esp32c6::spi1::spi_mem_ctrl::W

pub struct W(_);

Register SPI_MEM_CTRL writer

Implementations

impl W

pub fn spi_mem_fdummy_rin(&mut self) -> SPI_MEM_FDUMMY_RIN_W<'_, 2>

Bit 2 - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller.

pub fn spi_mem_fdummy_wout(&mut self) -> SPI_MEM_FDUMMY_WOUT_W<'_, 3>

Bit 3 - In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller.

pub fn spi_mem_fcmd_quad(&mut self) -> SPI_MEM_FCMD_QUAD_W<'_, 8>

Bit 8 - Apply 4 signals during command phase 1:enable 0: disable

pub fn spi_mem_fastrd_mode(&mut self) -> SPI_MEM_FASTRD_MODE_W<'_, 13>

Bit 13 - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.

pub fn spi_mem_fread_dual(&mut self) -> SPI_MEM_FREAD_DUAL_W<'_, 14>

Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.

pub fn spi_mem_resandres(&mut self) -> SPI_MEM_RESANDRES_W<'_, 15>

Bit 15 - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.

pub fn spi_mem_q_pol(&mut self) -> SPI_MEM_Q_POL_W<'_, 18>

Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low

pub fn spi_mem_d_pol(&mut self) -> SPI_MEM_D_POL_W<'_, 19>

Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low

pub fn spi_mem_fread_quad(&mut self) -> SPI_MEM_FREAD_QUAD_W<'_, 20>

Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable.

pub fn spi_mem_wp(&mut self) -> SPI_MEM_WP_W<'_, 21>

Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low.

pub fn spi_mem_wrsr_2b(&mut self) -> SPI_MEM_WRSR_2B_W<'_, 22>

Bit 22 - two bytes data will be written to status register when it is set. 1: enable 0: disable.

pub fn spi_mem_fread_dio(&mut self) -> SPI_MEM_FREAD_DIO_W<'_, 23>

Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.

pub fn spi_mem_fread_qio(&mut self) -> SPI_MEM_FREAD_QIO_W<'_, 24>

Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<SPI_MEM_CTRL_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<SPI_MEM_CTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<SPI_MEM_CTRL_SPEC>> for W

fn from(writer: W<SPI_MEM_CTRL_SPEC>) -> Self

Converts to this type from the input type.