esp32c6/extmem/
l2_cache_acs_cnt_int_st.rs

1#[doc = "Register `L2_CACHE_ACS_CNT_INT_ST` reader"]
2pub type R = crate::R<L2_CACHE_ACS_CNT_INT_ST_SPEC>;
3#[doc = "Field `L2_IBUS0_OVF_INT_ST` reader - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache."]
4pub type L2_IBUS0_OVF_INT_ST_R = crate::BitReader;
5#[doc = "Field `L2_IBUS1_OVF_INT_ST` reader - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache."]
6pub type L2_IBUS1_OVF_INT_ST_R = crate::BitReader;
7#[doc = "Field `L2_IBUS2_OVF_INT_ST` reader - Reserved"]
8pub type L2_IBUS2_OVF_INT_ST_R = crate::BitReader;
9#[doc = "Field `L2_IBUS3_OVF_INT_ST` reader - Reserved"]
10pub type L2_IBUS3_OVF_INT_ST_R = crate::BitReader;
11#[doc = "Field `L2_DBUS0_OVF_INT_ST` reader - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache."]
12pub type L2_DBUS0_OVF_INT_ST_R = crate::BitReader;
13#[doc = "Field `L2_DBUS1_OVF_INT_ST` reader - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache."]
14pub type L2_DBUS1_OVF_INT_ST_R = crate::BitReader;
15#[doc = "Field `L2_DBUS2_OVF_INT_ST` reader - Reserved"]
16pub type L2_DBUS2_OVF_INT_ST_R = crate::BitReader;
17#[doc = "Field `L2_DBUS3_OVF_INT_ST` reader - Reserved"]
18pub type L2_DBUS3_OVF_INT_ST_R = crate::BitReader;
19impl R {
20    #[doc = "Bit 8 - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache."]
21    #[inline(always)]
22    pub fn l2_ibus0_ovf_int_st(&self) -> L2_IBUS0_OVF_INT_ST_R {
23        L2_IBUS0_OVF_INT_ST_R::new(((self.bits >> 8) & 1) != 0)
24    }
25    #[doc = "Bit 9 - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache."]
26    #[inline(always)]
27    pub fn l2_ibus1_ovf_int_st(&self) -> L2_IBUS1_OVF_INT_ST_R {
28        L2_IBUS1_OVF_INT_ST_R::new(((self.bits >> 9) & 1) != 0)
29    }
30    #[doc = "Bit 10 - Reserved"]
31    #[inline(always)]
32    pub fn l2_ibus2_ovf_int_st(&self) -> L2_IBUS2_OVF_INT_ST_R {
33        L2_IBUS2_OVF_INT_ST_R::new(((self.bits >> 10) & 1) != 0)
34    }
35    #[doc = "Bit 11 - Reserved"]
36    #[inline(always)]
37    pub fn l2_ibus3_ovf_int_st(&self) -> L2_IBUS3_OVF_INT_ST_R {
38        L2_IBUS3_OVF_INT_ST_R::new(((self.bits >> 11) & 1) != 0)
39    }
40    #[doc = "Bit 12 - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache."]
41    #[inline(always)]
42    pub fn l2_dbus0_ovf_int_st(&self) -> L2_DBUS0_OVF_INT_ST_R {
43        L2_DBUS0_OVF_INT_ST_R::new(((self.bits >> 12) & 1) != 0)
44    }
45    #[doc = "Bit 13 - The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache."]
46    #[inline(always)]
47    pub fn l2_dbus1_ovf_int_st(&self) -> L2_DBUS1_OVF_INT_ST_R {
48        L2_DBUS1_OVF_INT_ST_R::new(((self.bits >> 13) & 1) != 0)
49    }
50    #[doc = "Bit 14 - Reserved"]
51    #[inline(always)]
52    pub fn l2_dbus2_ovf_int_st(&self) -> L2_DBUS2_OVF_INT_ST_R {
53        L2_DBUS2_OVF_INT_ST_R::new(((self.bits >> 14) & 1) != 0)
54    }
55    #[doc = "Bit 15 - Reserved"]
56    #[inline(always)]
57    pub fn l2_dbus3_ovf_int_st(&self) -> L2_DBUS3_OVF_INT_ST_R {
58        L2_DBUS3_OVF_INT_ST_R::new(((self.bits >> 15) & 1) != 0)
59    }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64        f.debug_struct("L2_CACHE_ACS_CNT_INT_ST")
65            .field("l2_ibus0_ovf_int_st", &self.l2_ibus0_ovf_int_st())
66            .field("l2_ibus1_ovf_int_st", &self.l2_ibus1_ovf_int_st())
67            .field("l2_ibus2_ovf_int_st", &self.l2_ibus2_ovf_int_st())
68            .field("l2_ibus3_ovf_int_st", &self.l2_ibus3_ovf_int_st())
69            .field("l2_dbus0_ovf_int_st", &self.l2_dbus0_ovf_int_st())
70            .field("l2_dbus1_ovf_int_st", &self.l2_dbus1_ovf_int_st())
71            .field("l2_dbus2_ovf_int_st", &self.l2_dbus2_ovf_int_st())
72            .field("l2_dbus3_ovf_int_st", &self.l2_dbus3_ovf_int_st())
73            .finish()
74    }
75}
76#[doc = "Cache Access Counter Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`l2_cache_acs_cnt_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct L2_CACHE_ACS_CNT_INT_ST_SPEC;
78impl crate::RegisterSpec for L2_CACHE_ACS_CNT_INT_ST_SPEC {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`l2_cache_acs_cnt_int_st::R`](R) reader structure"]
82impl crate::Readable for L2_CACHE_ACS_CNT_INT_ST_SPEC {}
83#[doc = "`reset()` method sets L2_CACHE_ACS_CNT_INT_ST to value 0"]
84impl crate::Resettable for L2_CACHE_ACS_CNT_INT_ST_SPEC {}
esp32c6/extmem/l2_cache_acs_cnt_int_st.rs

esp32c6/extmem/
l2_cache_acs_cnt_int_st.rs
