esp32c6/extmem/
level_split0.rs

1#[doc = "Register `LEVEL_SPLIT0` reader"]
2pub type R = crate::R<LEVEL_SPLIT0_SPEC>;
3#[doc = "Field `LEVEL_SPLIT0` reader - Reserved"]
4pub type LEVEL_SPLIT0_R = crate::FieldReader<u32>;
5impl R {
6    #[doc = "Bits 0:31 - Reserved"]
7    #[inline(always)]
8    pub fn level_split0(&self) -> LEVEL_SPLIT0_R {
9        LEVEL_SPLIT0_R::new(self.bits)
10    }
11}
12#[cfg(feature = "impl-register-debug")]
13impl core::fmt::Debug for R {
14    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
15        f.debug_struct("LEVEL_SPLIT0")
16            .field("level_split0", &self.level_split0())
17            .finish()
18    }
19}
20#[doc = "USED TO SPLIT L1 CACHE AND L2 CACHE\n\nYou can [`read`](crate::Reg::read) this register and get [`level_split0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21pub struct LEVEL_SPLIT0_SPEC;
22impl crate::RegisterSpec for LEVEL_SPLIT0_SPEC {
23    type Ux = u32;
24}
25#[doc = "`read()` method returns [`level_split0::R`](R) reader structure"]
26impl crate::Readable for LEVEL_SPLIT0_SPEC {}
27#[doc = "`reset()` method sets LEVEL_SPLIT0 to value 0x0258"]
28impl crate::Resettable for LEVEL_SPLIT0_SPEC {
29    const RESET_VALUE: u32 = 0x0258;
30}
esp32c6/extmem/level_split0.rs

esp32c6/extmem/
level_split0.rs
