esp32c6/extmem/
l1_cache_acs_cnt_ctrl.rs

1#[doc = "Register `L1_CACHE_ACS_CNT_CTRL` reader"]
2pub type R = crate::R<L1_CACHE_ACS_CNT_CTRL_SPEC>;
3#[doc = "Register `L1_CACHE_ACS_CNT_CTRL` writer"]
4pub type W = crate::W<L1_CACHE_ACS_CNT_CTRL_SPEC>;
5#[doc = "Field `L1_IBUS0_CNT_ENA` reader - The bit is used to enable ibus0 counter in L1-ICache0."]
6pub type L1_IBUS0_CNT_ENA_R = crate::BitReader;
7#[doc = "Field `L1_IBUS1_CNT_ENA` reader - The bit is used to enable ibus1 counter in L1-ICache1."]
8pub type L1_IBUS1_CNT_ENA_R = crate::BitReader;
9#[doc = "Field `L1_IBUS2_CNT_ENA` reader - Reserved"]
10pub type L1_IBUS2_CNT_ENA_R = crate::BitReader;
11#[doc = "Field `L1_IBUS3_CNT_ENA` reader - Reserved"]
12pub type L1_IBUS3_CNT_ENA_R = crate::BitReader;
13#[doc = "Field `L1_BUS0_CNT_ENA` reader - The bit is used to enable dbus0 counter in L1-DCache."]
14pub type L1_BUS0_CNT_ENA_R = crate::BitReader;
15#[doc = "Field `L1_BUS0_CNT_ENA` writer - The bit is used to enable dbus0 counter in L1-DCache."]
16pub type L1_BUS0_CNT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `L1_BUS1_CNT_ENA` reader - The bit is used to enable dbus1 counter in L1-DCache."]
18pub type L1_BUS1_CNT_ENA_R = crate::BitReader;
19#[doc = "Field `L1_BUS1_CNT_ENA` writer - The bit is used to enable dbus1 counter in L1-DCache."]
20pub type L1_BUS1_CNT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `L1_DBUS2_CNT_ENA` reader - Reserved"]
22pub type L1_DBUS2_CNT_ENA_R = crate::BitReader;
23#[doc = "Field `L1_DBUS3_CNT_ENA` reader - Reserved"]
24pub type L1_DBUS3_CNT_ENA_R = crate::BitReader;
25#[doc = "Field `L1_IBUS0_CNT_CLR` reader - The bit is used to clear ibus0 counter in L1-ICache0."]
26pub type L1_IBUS0_CNT_CLR_R = crate::BitReader;
27#[doc = "Field `L1_IBUS1_CNT_CLR` reader - The bit is used to clear ibus1 counter in L1-ICache1."]
28pub type L1_IBUS1_CNT_CLR_R = crate::BitReader;
29#[doc = "Field `L1_IBUS2_CNT_CLR` reader - Reserved"]
30pub type L1_IBUS2_CNT_CLR_R = crate::BitReader;
31#[doc = "Field `L1_IBUS3_CNT_CLR` reader - Reserved"]
32pub type L1_IBUS3_CNT_CLR_R = crate::BitReader;
33#[doc = "Field `L1_BUS0_CNT_CLR` writer - The bit is used to clear dbus0 counter in L1-DCache."]
34pub type L1_BUS0_CNT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `L1_BUS1_CNT_CLR` writer - The bit is used to clear dbus1 counter in L1-DCache."]
36pub type L1_BUS1_CNT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `L1_DBUS2_CNT_CLR` reader - Reserved"]
38pub type L1_DBUS2_CNT_CLR_R = crate::BitReader;
39#[doc = "Field `L1_DBUS3_CNT_CLR` reader - Reserved"]
40pub type L1_DBUS3_CNT_CLR_R = crate::BitReader;
41impl R {
42    #[doc = "Bit 0 - The bit is used to enable ibus0 counter in L1-ICache0."]
43    #[inline(always)]
44    pub fn l1_ibus0_cnt_ena(&self) -> L1_IBUS0_CNT_ENA_R {
45        L1_IBUS0_CNT_ENA_R::new((self.bits & 1) != 0)
46    }
47    #[doc = "Bit 1 - The bit is used to enable ibus1 counter in L1-ICache1."]
48    #[inline(always)]
49    pub fn l1_ibus1_cnt_ena(&self) -> L1_IBUS1_CNT_ENA_R {
50        L1_IBUS1_CNT_ENA_R::new(((self.bits >> 1) & 1) != 0)
51    }
52    #[doc = "Bit 2 - Reserved"]
53    #[inline(always)]
54    pub fn l1_ibus2_cnt_ena(&self) -> L1_IBUS2_CNT_ENA_R {
55        L1_IBUS2_CNT_ENA_R::new(((self.bits >> 2) & 1) != 0)
56    }
57    #[doc = "Bit 3 - Reserved"]
58    #[inline(always)]
59    pub fn l1_ibus3_cnt_ena(&self) -> L1_IBUS3_CNT_ENA_R {
60        L1_IBUS3_CNT_ENA_R::new(((self.bits >> 3) & 1) != 0)
61    }
62    #[doc = "Bit 4 - The bit is used to enable dbus0 counter in L1-DCache."]
63    #[inline(always)]
64    pub fn l1_bus0_cnt_ena(&self) -> L1_BUS0_CNT_ENA_R {
65        L1_BUS0_CNT_ENA_R::new(((self.bits >> 4) & 1) != 0)
66    }
67    #[doc = "Bit 5 - The bit is used to enable dbus1 counter in L1-DCache."]
68    #[inline(always)]
69    pub fn l1_bus1_cnt_ena(&self) -> L1_BUS1_CNT_ENA_R {
70        L1_BUS1_CNT_ENA_R::new(((self.bits >> 5) & 1) != 0)
71    }
72    #[doc = "Bit 6 - Reserved"]
73    #[inline(always)]
74    pub fn l1_dbus2_cnt_ena(&self) -> L1_DBUS2_CNT_ENA_R {
75        L1_DBUS2_CNT_ENA_R::new(((self.bits >> 6) & 1) != 0)
76    }
77    #[doc = "Bit 7 - Reserved"]
78    #[inline(always)]
79    pub fn l1_dbus3_cnt_ena(&self) -> L1_DBUS3_CNT_ENA_R {
80        L1_DBUS3_CNT_ENA_R::new(((self.bits >> 7) & 1) != 0)
81    }
82    #[doc = "Bit 16 - The bit is used to clear ibus0 counter in L1-ICache0."]
83    #[inline(always)]
84    pub fn l1_ibus0_cnt_clr(&self) -> L1_IBUS0_CNT_CLR_R {
85        L1_IBUS0_CNT_CLR_R::new(((self.bits >> 16) & 1) != 0)
86    }
87    #[doc = "Bit 17 - The bit is used to clear ibus1 counter in L1-ICache1."]
88    #[inline(always)]
89    pub fn l1_ibus1_cnt_clr(&self) -> L1_IBUS1_CNT_CLR_R {
90        L1_IBUS1_CNT_CLR_R::new(((self.bits >> 17) & 1) != 0)
91    }
92    #[doc = "Bit 18 - Reserved"]
93    #[inline(always)]
94    pub fn l1_ibus2_cnt_clr(&self) -> L1_IBUS2_CNT_CLR_R {
95        L1_IBUS2_CNT_CLR_R::new(((self.bits >> 18) & 1) != 0)
96    }
97    #[doc = "Bit 19 - Reserved"]
98    #[inline(always)]
99    pub fn l1_ibus3_cnt_clr(&self) -> L1_IBUS3_CNT_CLR_R {
100        L1_IBUS3_CNT_CLR_R::new(((self.bits >> 19) & 1) != 0)
101    }
102    #[doc = "Bit 22 - Reserved"]
103    #[inline(always)]
104    pub fn l1_dbus2_cnt_clr(&self) -> L1_DBUS2_CNT_CLR_R {
105        L1_DBUS2_CNT_CLR_R::new(((self.bits >> 22) & 1) != 0)
106    }
107    #[doc = "Bit 23 - Reserved"]
108    #[inline(always)]
109    pub fn l1_dbus3_cnt_clr(&self) -> L1_DBUS3_CNT_CLR_R {
110        L1_DBUS3_CNT_CLR_R::new(((self.bits >> 23) & 1) != 0)
111    }
112}
113#[cfg(feature = "impl-register-debug")]
114impl core::fmt::Debug for R {
115    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
116        f.debug_struct("L1_CACHE_ACS_CNT_CTRL")
117            .field("l1_ibus0_cnt_ena", &self.l1_ibus0_cnt_ena())
118            .field("l1_ibus1_cnt_ena", &self.l1_ibus1_cnt_ena())
119            .field("l1_ibus2_cnt_ena", &self.l1_ibus2_cnt_ena())
120            .field("l1_ibus3_cnt_ena", &self.l1_ibus3_cnt_ena())
121            .field("l1_bus0_cnt_ena", &self.l1_bus0_cnt_ena())
122            .field("l1_bus1_cnt_ena", &self.l1_bus1_cnt_ena())
123            .field("l1_dbus2_cnt_ena", &self.l1_dbus2_cnt_ena())
124            .field("l1_dbus3_cnt_ena", &self.l1_dbus3_cnt_ena())
125            .field("l1_ibus0_cnt_clr", &self.l1_ibus0_cnt_clr())
126            .field("l1_ibus1_cnt_clr", &self.l1_ibus1_cnt_clr())
127            .field("l1_ibus2_cnt_clr", &self.l1_ibus2_cnt_clr())
128            .field("l1_ibus3_cnt_clr", &self.l1_ibus3_cnt_clr())
129            .field("l1_dbus2_cnt_clr", &self.l1_dbus2_cnt_clr())
130            .field("l1_dbus3_cnt_clr", &self.l1_dbus3_cnt_clr())
131            .finish()
132    }
133}
134impl W {
135    #[doc = "Bit 4 - The bit is used to enable dbus0 counter in L1-DCache."]
136    #[inline(always)]
137    pub fn l1_bus0_cnt_ena(&mut self) -> L1_BUS0_CNT_ENA_W<L1_CACHE_ACS_CNT_CTRL_SPEC> {
138        L1_BUS0_CNT_ENA_W::new(self, 4)
139    }
140    #[doc = "Bit 5 - The bit is used to enable dbus1 counter in L1-DCache."]
141    #[inline(always)]
142    pub fn l1_bus1_cnt_ena(&mut self) -> L1_BUS1_CNT_ENA_W<L1_CACHE_ACS_CNT_CTRL_SPEC> {
143        L1_BUS1_CNT_ENA_W::new(self, 5)
144    }
145    #[doc = "Bit 20 - The bit is used to clear dbus0 counter in L1-DCache."]
146    #[inline(always)]
147    pub fn l1_bus0_cnt_clr(&mut self) -> L1_BUS0_CNT_CLR_W<L1_CACHE_ACS_CNT_CTRL_SPEC> {
148        L1_BUS0_CNT_CLR_W::new(self, 20)
149    }
150    #[doc = "Bit 21 - The bit is used to clear dbus1 counter in L1-DCache."]
151    #[inline(always)]
152    pub fn l1_bus1_cnt_clr(&mut self) -> L1_BUS1_CNT_CLR_W<L1_CACHE_ACS_CNT_CTRL_SPEC> {
153        L1_BUS1_CNT_CLR_W::new(self, 21)
154    }
155}
156#[doc = "Cache Access Counter enable and clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`l1_cache_acs_cnt_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`l1_cache_acs_cnt_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
157pub struct L1_CACHE_ACS_CNT_CTRL_SPEC;
158impl crate::RegisterSpec for L1_CACHE_ACS_CNT_CTRL_SPEC {
159    type Ux = u32;
160}
161#[doc = "`read()` method returns [`l1_cache_acs_cnt_ctrl::R`](R) reader structure"]
162impl crate::Readable for L1_CACHE_ACS_CNT_CTRL_SPEC {}
163#[doc = "`write(|w| ..)` method takes [`l1_cache_acs_cnt_ctrl::W`](W) writer structure"]
164impl crate::Writable for L1_CACHE_ACS_CNT_CTRL_SPEC {
165    type Safety = crate::Unsafe;
166}
167#[doc = "`reset()` method sets L1_CACHE_ACS_CNT_CTRL to value 0"]
168impl crate::Resettable for L1_CACHE_ACS_CNT_CTRL_SPEC {}
esp32c6/extmem/l1_cache_acs_cnt_ctrl.rs

esp32c6/extmem/
l1_cache_acs_cnt_ctrl.rs
