Module regclk

Timer group clock gate register

Structs

REGCLK_SPEC

Timer group clock gate register

Type Aliases

CLK_EN_R

Field CLK_EN reader - Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software.

CLK_EN_W

Field CLK_EN writer - Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software.

ETM_EN_R

Field ETM_EN reader - enable timer’s etm task and event

ETM_EN_W

Field ETM_EN writer - enable timer’s etm task and event

R

Register REGCLK reader

TIMER_CLK_IS_ACTIVE_R

Field TIMER_CLK_IS_ACTIVE reader - enable Timer 30’s clock

TIMER_CLK_IS_ACTIVE_W

Field TIMER_CLK_IS_ACTIVE writer - enable Timer 30’s clock

W

Register REGCLK writer

WDT_CLK_IS_ACTIVE_R

Field WDT_CLK_IS_ACTIVE reader - enable WDT’s clock

WDT_CLK_IS_ACTIVE_W

Field WDT_CLK_IS_ACTIVE writer - enable WDT’s clock