esp32c6/timg0/
regclk.rs

1#[doc = "Register `REGCLK` reader"]
2pub type R = crate::R<REGCLK_SPEC>;
3#[doc = "Register `REGCLK` writer"]
4pub type W = crate::W<REGCLK_SPEC>;
5#[doc = "Field `ETM_EN` reader - enable timer's etm task and event"]
6pub type ETM_EN_R = crate::BitReader;
7#[doc = "Field `ETM_EN` writer - enable timer's etm task and event"]
8pub type ETM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `WDT_CLK_IS_ACTIVE` reader - enable WDT's clock"]
10pub type WDT_CLK_IS_ACTIVE_R = crate::BitReader;
11#[doc = "Field `WDT_CLK_IS_ACTIVE` writer - enable WDT's clock"]
12pub type WDT_CLK_IS_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `TIMER_CLK_IS_ACTIVE` reader - enable Timer 30's clock"]
14pub type TIMER_CLK_IS_ACTIVE_R = crate::BitReader;
15#[doc = "Field `TIMER_CLK_IS_ACTIVE` writer - enable Timer 30's clock"]
16pub type TIMER_CLK_IS_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CLK_EN` reader - Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software."]
18pub type CLK_EN_R = crate::BitReader;
19#[doc = "Field `CLK_EN` writer - Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software."]
20pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 28 - enable timer's etm task and event"]
23    #[inline(always)]
24    pub fn etm_en(&self) -> ETM_EN_R {
25        ETM_EN_R::new(((self.bits >> 28) & 1) != 0)
26    }
27    #[doc = "Bit 29 - enable WDT's clock"]
28    #[inline(always)]
29    pub fn wdt_clk_is_active(&self) -> WDT_CLK_IS_ACTIVE_R {
30        WDT_CLK_IS_ACTIVE_R::new(((self.bits >> 29) & 1) != 0)
31    }
32    #[doc = "Bit 30 - enable Timer 30's clock"]
33    #[inline(always)]
34    pub fn timer_clk_is_active(&self) -> TIMER_CLK_IS_ACTIVE_R {
35        TIMER_CLK_IS_ACTIVE_R::new(((self.bits >> 30) & 1) != 0)
36    }
37    #[doc = "Bit 31 - Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software."]
38    #[inline(always)]
39    pub fn clk_en(&self) -> CLK_EN_R {
40        CLK_EN_R::new(((self.bits >> 31) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("REGCLK")
47            .field("etm_en", &self.etm_en())
48            .field("wdt_clk_is_active", &self.wdt_clk_is_active())
49            .field("timer_clk_is_active", &self.timer_clk_is_active())
50            .field("clk_en", &self.clk_en())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bit 28 - enable timer's etm task and event"]
56    #[inline(always)]
57    pub fn etm_en(&mut self) -> ETM_EN_W<REGCLK_SPEC> {
58        ETM_EN_W::new(self, 28)
59    }
60    #[doc = "Bit 29 - enable WDT's clock"]
61    #[inline(always)]
62    pub fn wdt_clk_is_active(&mut self) -> WDT_CLK_IS_ACTIVE_W<REGCLK_SPEC> {
63        WDT_CLK_IS_ACTIVE_W::new(self, 29)
64    }
65    #[doc = "Bit 30 - enable Timer 30's clock"]
66    #[inline(always)]
67    pub fn timer_clk_is_active(&mut self) -> TIMER_CLK_IS_ACTIVE_W<REGCLK_SPEC> {
68        TIMER_CLK_IS_ACTIVE_W::new(self, 30)
69    }
70    #[doc = "Bit 31 - Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software."]
71    #[inline(always)]
72    pub fn clk_en(&mut self) -> CLK_EN_W<REGCLK_SPEC> {
73        CLK_EN_W::new(self, 31)
74    }
75}
76#[doc = "Timer group clock gate register\n\nYou can [`read`](crate::Reg::read) this register and get [`regclk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`regclk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct REGCLK_SPEC;
78impl crate::RegisterSpec for REGCLK_SPEC {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`regclk::R`](R) reader structure"]
82impl crate::Readable for REGCLK_SPEC {}
83#[doc = "`write(|w| ..)` method takes [`regclk::W`](W) writer structure"]
84impl crate::Writable for REGCLK_SPEC {
85    type Safety = crate::Unsafe;
86}
87#[doc = "`reset()` method sets REGCLK to value 0x7000_0000"]
88impl crate::Resettable for REGCLK_SPEC {
89    const RESET_VALUE: u32 = 0x7000_0000;
90}
esp32c6/timg0/regclk.rs

esp32c6/timg0/
regclk.rs
