esp32c6/extmem/
l1_cache_acs_fail_id_attr.rs

1#[doc = "Register `L1_CACHE_ACS_FAIL_ID_ATTR` reader"]
2pub type R = crate::R<L1_CACHE_ACS_FAIL_ID_ATTR_SPEC>;
3#[doc = "Field `L1_CACHE_FAIL_ID` reader - The register records the ID of fail-access when cache accesses L1-Cache."]
4pub type L1_CACHE_FAIL_ID_R = crate::FieldReader<u16>;
5#[doc = "Field `L1_CACHE_FAIL_ATTR` reader - The register records the attribution of fail-access when cache accesses L1-Cache."]
6pub type L1_CACHE_FAIL_ATTR_R = crate::FieldReader<u16>;
7impl R {
8    #[doc = "Bits 0:15 - The register records the ID of fail-access when cache accesses L1-Cache."]
9    #[inline(always)]
10    pub fn l1_cache_fail_id(&self) -> L1_CACHE_FAIL_ID_R {
11        L1_CACHE_FAIL_ID_R::new((self.bits & 0xffff) as u16)
12    }
13    #[doc = "Bits 16:31 - The register records the attribution of fail-access when cache accesses L1-Cache."]
14    #[inline(always)]
15    pub fn l1_cache_fail_attr(&self) -> L1_CACHE_FAIL_ATTR_R {
16        L1_CACHE_FAIL_ATTR_R::new(((self.bits >> 16) & 0xffff) as u16)
17    }
18}
19#[cfg(feature = "impl-register-debug")]
20impl core::fmt::Debug for R {
21    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22        f.debug_struct("L1_CACHE_ACS_FAIL_ID_ATTR")
23            .field("l1_cache_fail_id", &self.l1_cache_fail_id())
24            .field("l1_cache_fail_attr", &self.l1_cache_fail_attr())
25            .finish()
26    }
27}
28#[doc = "L1-Cache Access Fail ID/attribution information register\n\nYou can [`read`](crate::Reg::read) this register and get [`l1_cache_acs_fail_id_attr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29pub struct L1_CACHE_ACS_FAIL_ID_ATTR_SPEC;
30impl crate::RegisterSpec for L1_CACHE_ACS_FAIL_ID_ATTR_SPEC {
31    type Ux = u32;
32}
33#[doc = "`read()` method returns [`l1_cache_acs_fail_id_attr::R`](R) reader structure"]
34impl crate::Readable for L1_CACHE_ACS_FAIL_ID_ATTR_SPEC {}
35#[doc = "`reset()` method sets L1_CACHE_ACS_FAIL_ID_ATTR to value 0"]
36impl crate::Resettable for L1_CACHE_ACS_FAIL_ID_ATTR_SPEC {}
esp32c6/extmem/l1_cache_acs_fail_id_attr.rs

esp32c6/extmem/
l1_cache_acs_fail_id_attr.rs
