1#[doc = "Register `CONF1` reader"]
2pub type R = crate::R<CONF1_SPEC>;
3#[doc = "Register `CONF1` writer"]
4pub type W = crate::W<CONF1_SPEC>;
5#[doc = "Field `CHECK_SUM_EN` reader - Set this bit to enable head checksum check when receiving."]
6pub type CHECK_SUM_EN_R = crate::BitReader;
7#[doc = "Field `CHECK_SUM_EN` writer - Set this bit to enable head checksum check when receiving."]
8pub type CHECK_SUM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CHECK_SEQ_EN` reader - Set this bit to enable sequence number check when receiving."]
10pub type CHECK_SEQ_EN_R = crate::BitReader;
11#[doc = "Field `CHECK_SEQ_EN` writer - Set this bit to enable sequence number check when receiving."]
12pub type CHECK_SEQ_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CRC_DISABLE` reader - Set this bit to support CRC calculation, and data integrity check bit should 1."]
14pub type CRC_DISABLE_R = crate::BitReader;
15#[doc = "Field `CRC_DISABLE` writer - Set this bit to support CRC calculation, and data integrity check bit should 1."]
16pub type CRC_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SAVE_HEAD` reader - Set this bit to save data packet head when UHCI receive data."]
18pub type SAVE_HEAD_R = crate::BitReader;
19#[doc = "Field `SAVE_HEAD` writer - Set this bit to save data packet head when UHCI receive data."]
20pub type SAVE_HEAD_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TX_CHECK_SUM_RE` reader - Set this bit to encode data packet with checksum."]
22pub type TX_CHECK_SUM_RE_R = crate::BitReader;
23#[doc = "Field `TX_CHECK_SUM_RE` writer - Set this bit to encode data packet with checksum."]
24pub type TX_CHECK_SUM_RE_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `TX_ACK_NUM_RE` reader - Set this bit to encode data packet with ACK when reliable data packet is ready."]
26pub type TX_ACK_NUM_RE_R = crate::BitReader;
27#[doc = "Field `TX_ACK_NUM_RE` writer - Set this bit to encode data packet with ACK when reliable data packet is ready."]
28pub type TX_ACK_NUM_RE_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `WAIT_SW_START` reader - Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status."]
30pub type WAIT_SW_START_R = crate::BitReader;
31#[doc = "Field `WAIT_SW_START` writer - Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status."]
32pub type WAIT_SW_START_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `SW_START` writer - Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT."]
34pub type SW_START_W<'a, REG> = crate::BitWriter<'a, REG>;
35impl R {
36 #[doc = "Bit 0 - Set this bit to enable head checksum check when receiving."]
37 #[inline(always)]
38 pub fn check_sum_en(&self) -> CHECK_SUM_EN_R {
39 CHECK_SUM_EN_R::new((self.bits & 1) != 0)
40 }
41 #[doc = "Bit 1 - Set this bit to enable sequence number check when receiving."]
42 #[inline(always)]
43 pub fn check_seq_en(&self) -> CHECK_SEQ_EN_R {
44 CHECK_SEQ_EN_R::new(((self.bits >> 1) & 1) != 0)
45 }
46 #[doc = "Bit 2 - Set this bit to support CRC calculation, and data integrity check bit should 1."]
47 #[inline(always)]
48 pub fn crc_disable(&self) -> CRC_DISABLE_R {
49 CRC_DISABLE_R::new(((self.bits >> 2) & 1) != 0)
50 }
51 #[doc = "Bit 3 - Set this bit to save data packet head when UHCI receive data."]
52 #[inline(always)]
53 pub fn save_head(&self) -> SAVE_HEAD_R {
54 SAVE_HEAD_R::new(((self.bits >> 3) & 1) != 0)
55 }
56 #[doc = "Bit 4 - Set this bit to encode data packet with checksum."]
57 #[inline(always)]
58 pub fn tx_check_sum_re(&self) -> TX_CHECK_SUM_RE_R {
59 TX_CHECK_SUM_RE_R::new(((self.bits >> 4) & 1) != 0)
60 }
61 #[doc = "Bit 5 - Set this bit to encode data packet with ACK when reliable data packet is ready."]
62 #[inline(always)]
63 pub fn tx_ack_num_re(&self) -> TX_ACK_NUM_RE_R {
64 TX_ACK_NUM_RE_R::new(((self.bits >> 5) & 1) != 0)
65 }
66 #[doc = "Bit 7 - Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status."]
67 #[inline(always)]
68 pub fn wait_sw_start(&self) -> WAIT_SW_START_R {
69 WAIT_SW_START_R::new(((self.bits >> 7) & 1) != 0)
70 }
71}
72#[cfg(feature = "impl-register-debug")]
73impl core::fmt::Debug for R {
74 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
75 f.debug_struct("CONF1")
76 .field("check_sum_en", &self.check_sum_en())
77 .field("check_seq_en", &self.check_seq_en())
78 .field("crc_disable", &self.crc_disable())
79 .field("save_head", &self.save_head())
80 .field("tx_check_sum_re", &self.tx_check_sum_re())
81 .field("tx_ack_num_re", &self.tx_ack_num_re())
82 .field("wait_sw_start", &self.wait_sw_start())
83 .finish()
84 }
85}
86impl W {
87 #[doc = "Bit 0 - Set this bit to enable head checksum check when receiving."]
88 #[inline(always)]
89 pub fn check_sum_en(&mut self) -> CHECK_SUM_EN_W<CONF1_SPEC> {
90 CHECK_SUM_EN_W::new(self, 0)
91 }
92 #[doc = "Bit 1 - Set this bit to enable sequence number check when receiving."]
93 #[inline(always)]
94 pub fn check_seq_en(&mut self) -> CHECK_SEQ_EN_W<CONF1_SPEC> {
95 CHECK_SEQ_EN_W::new(self, 1)
96 }
97 #[doc = "Bit 2 - Set this bit to support CRC calculation, and data integrity check bit should 1."]
98 #[inline(always)]
99 pub fn crc_disable(&mut self) -> CRC_DISABLE_W<CONF1_SPEC> {
100 CRC_DISABLE_W::new(self, 2)
101 }
102 #[doc = "Bit 3 - Set this bit to save data packet head when UHCI receive data."]
103 #[inline(always)]
104 pub fn save_head(&mut self) -> SAVE_HEAD_W<CONF1_SPEC> {
105 SAVE_HEAD_W::new(self, 3)
106 }
107 #[doc = "Bit 4 - Set this bit to encode data packet with checksum."]
108 #[inline(always)]
109 pub fn tx_check_sum_re(&mut self) -> TX_CHECK_SUM_RE_W<CONF1_SPEC> {
110 TX_CHECK_SUM_RE_W::new(self, 4)
111 }
112 #[doc = "Bit 5 - Set this bit to encode data packet with ACK when reliable data packet is ready."]
113 #[inline(always)]
114 pub fn tx_ack_num_re(&mut self) -> TX_ACK_NUM_RE_W<CONF1_SPEC> {
115 TX_ACK_NUM_RE_W::new(self, 5)
116 }
117 #[doc = "Bit 7 - Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status."]
118 #[inline(always)]
119 pub fn wait_sw_start(&mut self) -> WAIT_SW_START_W<CONF1_SPEC> {
120 WAIT_SW_START_W::new(self, 7)
121 }
122 #[doc = "Bit 8 - Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT."]
123 #[inline(always)]
124 pub fn sw_start(&mut self) -> SW_START_W<CONF1_SPEC> {
125 SW_START_W::new(self, 8)
126 }
127}
128#[doc = "UHCI Configuration Register1\n\nYou can [`read`](crate::Reg::read) this register and get [`conf1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
129pub struct CONF1_SPEC;
130impl crate::RegisterSpec for CONF1_SPEC {
131 type Ux = u32;
132}
133#[doc = "`read()` method returns [`conf1::R`](R) reader structure"]
134impl crate::Readable for CONF1_SPEC {}
135#[doc = "`write(|w| ..)` method takes [`conf1::W`](W) writer structure"]
136impl crate::Writable for CONF1_SPEC {
137 type Safety = crate::Unsafe;
138 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
139 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
140}
141#[doc = "`reset()` method sets CONF1 to value 0x33"]
142impl crate::Resettable for CONF1_SPEC {
143 const RESET_VALUE: u32 = 0x33;
144}