esp32c6/usb_device/
int_clr.rs

1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `JTAG_IN_FLUSH` writer - Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt."]
4pub type JTAG_IN_FLUSH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `SOF` writer - Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt."]
6pub type SOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `SERIAL_OUT_RECV_PKT` writer - Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt."]
8pub type SERIAL_OUT_RECV_PKT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `SERIAL_IN_EMPTY` writer - Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt."]
10pub type SERIAL_IN_EMPTY_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `PID_ERR` writer - Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt."]
12pub type PID_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `CRC5_ERR` writer - Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt."]
14pub type CRC5_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `CRC16_ERR` writer - Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt."]
16pub type CRC16_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `STUFF_ERR` writer - Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt."]
18pub type STUFF_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `IN_TOKEN_REC_IN_EP1` writer - Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt."]
20pub type IN_TOKEN_REC_IN_EP1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `USB_BUS_RESET` writer - Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt."]
22pub type USB_BUS_RESET_W<'a, REG> = crate::BitWriter1C<'a, REG>;
23#[doc = "Field `OUT_EP1_ZERO_PAYLOAD` writer - Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt."]
24pub type OUT_EP1_ZERO_PAYLOAD_W<'a, REG> = crate::BitWriter1C<'a, REG>;
25#[doc = "Field `OUT_EP2_ZERO_PAYLOAD` writer - Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt."]
26pub type OUT_EP2_ZERO_PAYLOAD_W<'a, REG> = crate::BitWriter1C<'a, REG>;
27#[doc = "Field `RTS_CHG` writer - Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt."]
28pub type RTS_CHG_W<'a, REG> = crate::BitWriter1C<'a, REG>;
29#[doc = "Field `DTR_CHG` writer - Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt."]
30pub type DTR_CHG_W<'a, REG> = crate::BitWriter1C<'a, REG>;
31#[doc = "Field `GET_LINE_CODE` writer - Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt."]
32pub type GET_LINE_CODE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
33#[doc = "Field `SET_LINE_CODE` writer - Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt."]
34pub type SET_LINE_CODE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
35#[cfg(feature = "impl-register-debug")]
36impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
37    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
38        write!(f, "(not readable)")
39    }
40}
41impl W {
42    #[doc = "Bit 0 - Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt."]
43    #[inline(always)]
44    pub fn jtag_in_flush(&mut self) -> JTAG_IN_FLUSH_W<INT_CLR_SPEC> {
45        JTAG_IN_FLUSH_W::new(self, 0)
46    }
47    #[doc = "Bit 1 - Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt."]
48    #[inline(always)]
49    pub fn sof(&mut self) -> SOF_W<INT_CLR_SPEC> {
50        SOF_W::new(self, 1)
51    }
52    #[doc = "Bit 2 - Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt."]
53    #[inline(always)]
54    pub fn serial_out_recv_pkt(&mut self) -> SERIAL_OUT_RECV_PKT_W<INT_CLR_SPEC> {
55        SERIAL_OUT_RECV_PKT_W::new(self, 2)
56    }
57    #[doc = "Bit 3 - Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt."]
58    #[inline(always)]
59    pub fn serial_in_empty(&mut self) -> SERIAL_IN_EMPTY_W<INT_CLR_SPEC> {
60        SERIAL_IN_EMPTY_W::new(self, 3)
61    }
62    #[doc = "Bit 4 - Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt."]
63    #[inline(always)]
64    pub fn pid_err(&mut self) -> PID_ERR_W<INT_CLR_SPEC> {
65        PID_ERR_W::new(self, 4)
66    }
67    #[doc = "Bit 5 - Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt."]
68    #[inline(always)]
69    pub fn crc5_err(&mut self) -> CRC5_ERR_W<INT_CLR_SPEC> {
70        CRC5_ERR_W::new(self, 5)
71    }
72    #[doc = "Bit 6 - Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt."]
73    #[inline(always)]
74    pub fn crc16_err(&mut self) -> CRC16_ERR_W<INT_CLR_SPEC> {
75        CRC16_ERR_W::new(self, 6)
76    }
77    #[doc = "Bit 7 - Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt."]
78    #[inline(always)]
79    pub fn stuff_err(&mut self) -> STUFF_ERR_W<INT_CLR_SPEC> {
80        STUFF_ERR_W::new(self, 7)
81    }
82    #[doc = "Bit 8 - Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt."]
83    #[inline(always)]
84    pub fn in_token_rec_in_ep1(&mut self) -> IN_TOKEN_REC_IN_EP1_W<INT_CLR_SPEC> {
85        IN_TOKEN_REC_IN_EP1_W::new(self, 8)
86    }
87    #[doc = "Bit 9 - Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt."]
88    #[inline(always)]
89    pub fn usb_bus_reset(&mut self) -> USB_BUS_RESET_W<INT_CLR_SPEC> {
90        USB_BUS_RESET_W::new(self, 9)
91    }
92    #[doc = "Bit 10 - Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt."]
93    #[inline(always)]
94    pub fn out_ep1_zero_payload(&mut self) -> OUT_EP1_ZERO_PAYLOAD_W<INT_CLR_SPEC> {
95        OUT_EP1_ZERO_PAYLOAD_W::new(self, 10)
96    }
97    #[doc = "Bit 11 - Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt."]
98    #[inline(always)]
99    pub fn out_ep2_zero_payload(&mut self) -> OUT_EP2_ZERO_PAYLOAD_W<INT_CLR_SPEC> {
100        OUT_EP2_ZERO_PAYLOAD_W::new(self, 11)
101    }
102    #[doc = "Bit 12 - Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt."]
103    #[inline(always)]
104    pub fn rts_chg(&mut self) -> RTS_CHG_W<INT_CLR_SPEC> {
105        RTS_CHG_W::new(self, 12)
106    }
107    #[doc = "Bit 13 - Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt."]
108    #[inline(always)]
109    pub fn dtr_chg(&mut self) -> DTR_CHG_W<INT_CLR_SPEC> {
110        DTR_CHG_W::new(self, 13)
111    }
112    #[doc = "Bit 14 - Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt."]
113    #[inline(always)]
114    pub fn get_line_code(&mut self) -> GET_LINE_CODE_W<INT_CLR_SPEC> {
115        GET_LINE_CODE_W::new(self, 14)
116    }
117    #[doc = "Bit 15 - Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt."]
118    #[inline(always)]
119    pub fn set_line_code(&mut self) -> SET_LINE_CODE_W<INT_CLR_SPEC> {
120        SET_LINE_CODE_W::new(self, 15)
121    }
122}
123#[doc = "Interrupt clear status register.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
124pub struct INT_CLR_SPEC;
125impl crate::RegisterSpec for INT_CLR_SPEC {
126    type Ux = u32;
127}
128#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
129impl crate::Writable for INT_CLR_SPEC {
130    type Safety = crate::Unsafe;
131    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
132    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff;
133}
134#[doc = "`reset()` method sets INT_CLR to value 0"]
135impl crate::Resettable for INT_CLR_SPEC {
136    const RESET_VALUE: u32 = 0;
137}
esp32c6/usb_device/int_clr.rs

esp32c6/usb_device/
int_clr.rs
