1#[doc = "Register `SRAM_CMD` reader"]
2pub type R = crate::R<SRAM_CMD_SPEC>;
3#[doc = "Register `SRAM_CMD` writer"]
4pub type W = crate::W<SRAM_CMD_SPEC>;
5#[doc = "Field `SCLK_MODE` reader - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on."]
6pub type SCLK_MODE_R = crate::FieldReader;
7#[doc = "Field `SWB_MODE` reader - Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit."]
8pub type SWB_MODE_R = crate::FieldReader;
9#[doc = "Field `SDIN_DUAL` reader - For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."]
10pub type SDIN_DUAL_R = crate::BitReader;
11#[doc = "Field `SDOUT_DUAL` reader - For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."]
12pub type SDOUT_DUAL_R = crate::BitReader;
13#[doc = "Field `SADDR_DUAL` reader - For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."]
14pub type SADDR_DUAL_R = crate::BitReader;
15#[doc = "Field `SDIN_QUAD` reader - For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
16pub type SDIN_QUAD_R = crate::BitReader;
17#[doc = "Field `SDOUT_QUAD` reader - For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
18pub type SDOUT_QUAD_R = crate::BitReader;
19#[doc = "Field `SADDR_QUAD` reader - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
20pub type SADDR_QUAD_R = crate::BitReader;
21#[doc = "Field `SCMD_QUAD` reader - For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
22pub type SCMD_QUAD_R = crate::BitReader;
23#[doc = "Field `SDIN_OCT` reader - For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable."]
24pub type SDIN_OCT_R = crate::BitReader;
25#[doc = "Field `SDOUT_OCT` reader - For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable."]
26pub type SDOUT_OCT_R = crate::BitReader;
27#[doc = "Field `SADDR_OCT` reader - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable."]
28pub type SADDR_OCT_R = crate::BitReader;
29#[doc = "Field `SCMD_OCT` reader - For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable."]
30pub type SCMD_OCT_R = crate::BitReader;
31#[doc = "Field `SDUMMY_RIN` reader - In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."]
32pub type SDUMMY_RIN_R = crate::BitReader;
33#[doc = "Field `SDUMMY_RIN` writer - In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."]
34pub type SDUMMY_RIN_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `SDUMMY_WOUT` reader - In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."]
36pub type SDUMMY_WOUT_R = crate::BitReader;
37#[doc = "Field `SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT` reader - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller."]
38pub type SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_R = crate::BitReader;
39#[doc = "Field `SPI_SMEM_WDUMMY_ALWAYS_OUT` reader - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO\\[7:0\\] is output by the MSPI controller."]
40pub type SPI_SMEM_WDUMMY_ALWAYS_OUT_R = crate::BitReader;
41#[doc = "Field `SPI_SMEM_DQS_IE_ALWAYS_ON` reader - When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others."]
42pub type SPI_SMEM_DQS_IE_ALWAYS_ON_R = crate::BitReader;
43#[doc = "Field `SPI_SMEM_DATA_IE_ALWAYS_ON` reader - When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO\\[7:0\\] are always 1. 0: Others."]
44pub type SPI_SMEM_DATA_IE_ALWAYS_ON_R = crate::BitReader;
45impl R {
46 #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on."]
47 #[inline(always)]
48 pub fn sclk_mode(&self) -> SCLK_MODE_R {
49 SCLK_MODE_R::new((self.bits & 3) as u8)
50 }
51 #[doc = "Bits 2:9 - Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit."]
52 #[inline(always)]
53 pub fn swb_mode(&self) -> SWB_MODE_R {
54 SWB_MODE_R::new(((self.bits >> 2) & 0xff) as u8)
55 }
56 #[doc = "Bit 10 - For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."]
57 #[inline(always)]
58 pub fn sdin_dual(&self) -> SDIN_DUAL_R {
59 SDIN_DUAL_R::new(((self.bits >> 10) & 1) != 0)
60 }
61 #[doc = "Bit 11 - For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."]
62 #[inline(always)]
63 pub fn sdout_dual(&self) -> SDOUT_DUAL_R {
64 SDOUT_DUAL_R::new(((self.bits >> 11) & 1) != 0)
65 }
66 #[doc = "Bit 12 - For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio."]
67 #[inline(always)]
68 pub fn saddr_dual(&self) -> SADDR_DUAL_R {
69 SADDR_DUAL_R::new(((self.bits >> 12) & 1) != 0)
70 }
71 #[doc = "Bit 14 - For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
72 #[inline(always)]
73 pub fn sdin_quad(&self) -> SDIN_QUAD_R {
74 SDIN_QUAD_R::new(((self.bits >> 14) & 1) != 0)
75 }
76 #[doc = "Bit 15 - For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
77 #[inline(always)]
78 pub fn sdout_quad(&self) -> SDOUT_QUAD_R {
79 SDOUT_QUAD_R::new(((self.bits >> 15) & 1) != 0)
80 }
81 #[doc = "Bit 16 - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
82 #[inline(always)]
83 pub fn saddr_quad(&self) -> SADDR_QUAD_R {
84 SADDR_QUAD_R::new(((self.bits >> 16) & 1) != 0)
85 }
86 #[doc = "Bit 17 - For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio."]
87 #[inline(always)]
88 pub fn scmd_quad(&self) -> SCMD_QUAD_R {
89 SCMD_QUAD_R::new(((self.bits >> 17) & 1) != 0)
90 }
91 #[doc = "Bit 18 - For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable."]
92 #[inline(always)]
93 pub fn sdin_oct(&self) -> SDIN_OCT_R {
94 SDIN_OCT_R::new(((self.bits >> 18) & 1) != 0)
95 }
96 #[doc = "Bit 19 - For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable."]
97 #[inline(always)]
98 pub fn sdout_oct(&self) -> SDOUT_OCT_R {
99 SDOUT_OCT_R::new(((self.bits >> 19) & 1) != 0)
100 }
101 #[doc = "Bit 20 - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable."]
102 #[inline(always)]
103 pub fn saddr_oct(&self) -> SADDR_OCT_R {
104 SADDR_OCT_R::new(((self.bits >> 20) & 1) != 0)
105 }
106 #[doc = "Bit 21 - For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable."]
107 #[inline(always)]
108 pub fn scmd_oct(&self) -> SCMD_OCT_R {
109 SCMD_OCT_R::new(((self.bits >> 21) & 1) != 0)
110 }
111 #[doc = "Bit 22 - In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."]
112 #[inline(always)]
113 pub fn sdummy_rin(&self) -> SDUMMY_RIN_R {
114 SDUMMY_RIN_R::new(((self.bits >> 22) & 1) != 0)
115 }
116 #[doc = "Bit 23 - In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."]
117 #[inline(always)]
118 pub fn sdummy_wout(&self) -> SDUMMY_WOUT_R {
119 SDUMMY_WOUT_R::new(((self.bits >> 23) & 1) != 0)
120 }
121 #[doc = "Bit 24 - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller."]
122 #[inline(always)]
123 pub fn spi_smem_wdummy_dqs_always_out(&self) -> SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_R {
124 SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_R::new(((self.bits >> 24) & 1) != 0)
125 }
126 #[doc = "Bit 25 - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO\\[7:0\\] is output by the MSPI controller."]
127 #[inline(always)]
128 pub fn spi_smem_wdummy_always_out(&self) -> SPI_SMEM_WDUMMY_ALWAYS_OUT_R {
129 SPI_SMEM_WDUMMY_ALWAYS_OUT_R::new(((self.bits >> 25) & 1) != 0)
130 }
131 #[doc = "Bit 30 - When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others."]
132 #[inline(always)]
133 pub fn spi_smem_dqs_ie_always_on(&self) -> SPI_SMEM_DQS_IE_ALWAYS_ON_R {
134 SPI_SMEM_DQS_IE_ALWAYS_ON_R::new(((self.bits >> 30) & 1) != 0)
135 }
136 #[doc = "Bit 31 - When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO\\[7:0\\] are always 1. 0: Others."]
137 #[inline(always)]
138 pub fn spi_smem_data_ie_always_on(&self) -> SPI_SMEM_DATA_IE_ALWAYS_ON_R {
139 SPI_SMEM_DATA_IE_ALWAYS_ON_R::new(((self.bits >> 31) & 1) != 0)
140 }
141}
142#[cfg(feature = "impl-register-debug")]
143impl core::fmt::Debug for R {
144 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
145 f.debug_struct("SRAM_CMD")
146 .field("sclk_mode", &self.sclk_mode())
147 .field("swb_mode", &self.swb_mode())
148 .field("sdin_dual", &self.sdin_dual())
149 .field("sdout_dual", &self.sdout_dual())
150 .field("saddr_dual", &self.saddr_dual())
151 .field("sdin_quad", &self.sdin_quad())
152 .field("sdout_quad", &self.sdout_quad())
153 .field("saddr_quad", &self.saddr_quad())
154 .field("scmd_quad", &self.scmd_quad())
155 .field("sdin_oct", &self.sdin_oct())
156 .field("sdout_oct", &self.sdout_oct())
157 .field("saddr_oct", &self.saddr_oct())
158 .field("scmd_oct", &self.scmd_oct())
159 .field("sdummy_rin", &self.sdummy_rin())
160 .field("sdummy_wout", &self.sdummy_wout())
161 .field(
162 "spi_smem_wdummy_dqs_always_out",
163 &self.spi_smem_wdummy_dqs_always_out(),
164 )
165 .field(
166 "spi_smem_wdummy_always_out",
167 &self.spi_smem_wdummy_always_out(),
168 )
169 .field(
170 "spi_smem_dqs_ie_always_on",
171 &self.spi_smem_dqs_ie_always_on(),
172 )
173 .field(
174 "spi_smem_data_ie_always_on",
175 &self.spi_smem_data_ie_always_on(),
176 )
177 .finish()
178 }
179}
180impl W {
181 #[doc = "Bit 22 - In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."]
182 #[inline(always)]
183 pub fn sdummy_rin(&mut self) -> SDUMMY_RIN_W<SRAM_CMD_SPEC> {
184 SDUMMY_RIN_W::new(self, 22)
185 }
186}
187#[doc = "SPI0 external RAM mode control register\n\nYou can [`read`](crate::Reg::read) this register and get [`sram_cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram_cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
188pub struct SRAM_CMD_SPEC;
189impl crate::RegisterSpec for SRAM_CMD_SPEC {
190 type Ux = u32;
191}
192#[doc = "`read()` method returns [`sram_cmd::R`](R) reader structure"]
193impl crate::Readable for SRAM_CMD_SPEC {}
194#[doc = "`write(|w| ..)` method takes [`sram_cmd::W`](W) writer structure"]
195impl crate::Writable for SRAM_CMD_SPEC {
196 type Safety = crate::Unsafe;
197 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
198 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
199}
200#[doc = "`reset()` method sets SRAM_CMD to value 0xc040_0000"]
201impl crate::Resettable for SRAM_CMD_SPEC {
202 const RESET_VALUE: u32 = 0xc040_0000;
203}