esp32c6/extmem/
l2_dbus2_acs_miss_cnt.rs

1#[doc = "Register `L2_DBUS2_ACS_MISS_CNT` reader"]
2pub type R = crate::R<L2_DBUS2_ACS_MISS_CNT_SPEC>;
3#[doc = "Field `L2_DBUS2_MISS_CNT` reader - The register records the number of missing when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache."]
4pub type L2_DBUS2_MISS_CNT_R = crate::FieldReader<u32>;
5impl R {
6    #[doc = "Bits 0:31 - The register records the number of missing when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache."]
7    #[inline(always)]
8    pub fn l2_dbus2_miss_cnt(&self) -> L2_DBUS2_MISS_CNT_R {
9        L2_DBUS2_MISS_CNT_R::new(self.bits)
10    }
11}
12#[cfg(feature = "impl-register-debug")]
13impl core::fmt::Debug for R {
14    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
15        f.debug_struct("L2_DBUS2_ACS_MISS_CNT")
16            .field("l2_dbus2_miss_cnt", &self.l2_dbus2_miss_cnt())
17            .finish()
18    }
19}
20#[doc = "L2-Cache bus2 Miss-Access Counter register\n\nYou can [`read`](crate::Reg::read) this register and get [`l2_dbus2_acs_miss_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
21pub struct L2_DBUS2_ACS_MISS_CNT_SPEC;
22impl crate::RegisterSpec for L2_DBUS2_ACS_MISS_CNT_SPEC {
23    type Ux = u32;
24}
25#[doc = "`read()` method returns [`l2_dbus2_acs_miss_cnt::R`](R) reader structure"]
26impl crate::Readable for L2_DBUS2_ACS_MISS_CNT_SPEC {}
27#[doc = "`reset()` method sets L2_DBUS2_ACS_MISS_CNT to value 0"]
28impl crate::Resettable for L2_DBUS2_ACS_MISS_CNT_SPEC {
29    const RESET_VALUE: u32 = 0;
30}
esp32c6/extmem/l2_dbus2_acs_miss_cnt.rs

esp32c6/extmem/
l2_dbus2_acs_miss_cnt.rs
