Type Alias W

pub type W = W<CACHE_FCTRL_SPEC>;

Register CACHE_FCTRL writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn axi_req_en(&mut self) -> AXI_REQ_EN_W<'_, CACHE_FCTRL_SPEC>

Bit 0 - For SPI0, AXI master access enable, 1: enable, 0:disable.

pub fn cache_usr_addr_4byte( &mut self, ) -> CACHE_USR_ADDR_4BYTE_W<'_, CACHE_FCTRL_SPEC>

Bit 1 - For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.

pub fn cache_flash_usr_cmd( &mut self, ) -> CACHE_FLASH_USR_CMD_W<'_, CACHE_FCTRL_SPEC>

Bit 2 - For SPI0, cache read flash for user define command, 1: enable, 0:disable.

pub fn fdin_dual(&mut self) -> FDIN_DUAL_W<'_, CACHE_FCTRL_SPEC>

Bit 3 - For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.

pub fn fdout_dual(&mut self) -> FDOUT_DUAL_W<'_, CACHE_FCTRL_SPEC>

Bit 4 - For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.

pub fn faddr_dual(&mut self) -> FADDR_DUAL_W<'_, CACHE_FCTRL_SPEC>

Bit 5 - For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.

pub fn fdin_quad(&mut self) -> FDIN_QUAD_W<'_, CACHE_FCTRL_SPEC>

Bit 6 - For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.

pub fn fdout_quad(&mut self) -> FDOUT_QUAD_W<'_, CACHE_FCTRL_SPEC>

Bit 7 - For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.

pub fn faddr_quad(&mut self) -> FADDR_QUAD_W<'_, CACHE_FCTRL_SPEC>

Bit 8 - For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.

pub fn spi_close_axi_inf_en( &mut self, ) -> SPI_CLOSE_AXI_INF_EN_W<'_, CACHE_FCTRL_SPEC>

Bit 31 - Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP.