Expand description
Configure 0 register of Tx channel 1
Structs§
- Configure 0 register of Tx channel 1
 
Type Aliases§
- Field
OUTDSCR_BURST_ENreader - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM. - Field
OUTDSCR_BURST_ENwriter - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM. - Field
OUT_AUTO_WRBACKreader - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. - Field
OUT_AUTO_WRBACKwriter - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. - Field
OUT_DATA_BURST_ENreader - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM. - Field
OUT_DATA_BURST_ENwriter - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM. - Field
OUT_EOF_MODEreader - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA - Field
OUT_EOF_MODEwriter - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA - Field
OUT_ETM_ENreader - Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm task. - Field
OUT_ETM_ENwriter - Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm task. - Field
OUT_LOOP_TESTreader - reserved - Field
OUT_LOOP_TESTwriter - reserved - Field
OUT_RSTreader - This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. - Field
OUT_RSTwriter - This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. - Register
OUT_CONF0reader - Register
OUT_CONF0writer