Type Alias esp32c6::spi0::sram_cmd::R

pub type R = R<SRAM_CMD_SPEC>;

Register SRAM_CMD reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn sclk_mode(&self) -> SCLK_MODE_R

Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.

pub fn swb_mode(&self) -> SWB_MODE_R

Bits 2:9 - Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit.

pub fn sdin_dual(&self) -> SDIN_DUAL_R

Bit 10 - For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.

pub fn sdout_dual(&self) -> SDOUT_DUAL_R

Bit 11 - For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.

pub fn saddr_dual(&self) -> SADDR_DUAL_R

Bit 12 - For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.

pub fn sdin_quad(&self) -> SDIN_QUAD_R

Bit 14 - For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.

pub fn sdout_quad(&self) -> SDOUT_QUAD_R

Bit 15 - For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.

pub fn saddr_quad(&self) -> SADDR_QUAD_R

Bit 16 - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.

pub fn scmd_quad(&self) -> SCMD_QUAD_R

Bit 17 - For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.

pub fn sdin_oct(&self) -> SDIN_OCT_R

Bit 18 - For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable.

pub fn sdout_oct(&self) -> SDOUT_OCT_R

Bit 19 - For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable.

pub fn saddr_oct(&self) -> SADDR_OCT_R

Bit 20 - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable.

pub fn scmd_oct(&self) -> SCMD_OCT_R

Bit 21 - For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable.

pub fn sdummy_rin(&self) -> SDUMMY_RIN_R

Bit 22 - In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.

pub fn sdummy_wout(&self) -> SDUMMY_WOUT_R

Bit 23 - In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.

pub fn spi_smem_wdummy_dqs_always_out(&self) -> SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_R

Bit 24 - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller.

pub fn spi_smem_wdummy_always_out(&self) -> SPI_SMEM_WDUMMY_ALWAYS_OUT_R

Bit 25 - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller.

pub fn spi_smem_dqs_ie_always_on(&self) -> SPI_SMEM_DQS_IE_ALWAYS_ON_R

Bit 30 - When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.

pub fn spi_smem_data_ie_always_on(&self) -> SPI_SMEM_DATA_IE_ALWAYS_ON_R

Bit 31 - When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.