Type Alias esp32c6::hinf::cfg_timing::W

pub type W = W<CFG_TIMING_SPEC>;

Register CFG_TIMING writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn ncrc(&mut self) -> NCRC_W<'_, CFG_TIMING_SPEC>

Bits 0:2 - configure Ncrc parameter in sdr50/104 mode, no more than 6.

pub fn pst_end_cmd_low_value( &mut self, ) -> PST_END_CMD_LOW_VALUE_W<'_, CFG_TIMING_SPEC>

Bits 3:9 - configure cycles to lower cmd after voltage is changed to 1.8V.

pub fn pst_end_data_low_value( &mut self, ) -> PST_END_DATA_LOW_VALUE_W<'_, CFG_TIMING_SPEC>

Bits 10:15 - configure cycles to lower data after voltage is changed to 1.8V.

pub fn sdclk_stop_thres(&mut self) -> SDCLK_STOP_THRES_W<'_, CFG_TIMING_SPEC>

Bits 16:26 - Configure the number of cycles of module clk to judge sdclk has stopped

pub fn sample_clk_divider( &mut self, ) -> SAMPLE_CLK_DIVIDER_W<'_, CFG_TIMING_SPEC>

Bits 28:31 - module clk divider to sample sdclk