Type Alias esp32c6::mcpwm0::cap_timer_cfg::W

pub type W = W<CAP_TIMER_CFG_SPEC>;

Register CAP_TIMER_CFG writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn cap_timer_en(&mut self) -> CAP_TIMER_EN_W<'_, CAP_TIMER_CFG_SPEC>

Bit 0 - When set, capture timer incrementing under APB_clk is enabled.

pub fn cap_synci_en(&mut self) -> CAP_SYNCI_EN_W<'_, CAP_TIMER_CFG_SPEC>

Bit 1 - When set, capture timer sync is enabled.

pub fn cap_synci_sel(&mut self) -> CAP_SYNCI_SEL_W<'_, CAP_TIMER_CFG_SPEC>

Bits 2:4 - capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix

pub fn cap_sync_sw(&mut self) -> CAP_SYNC_SW_W<'_, CAP_TIMER_CFG_SPEC>

Bit 5 - When reg_cap_synci_en is 1, write 1 will trigger a capture timer sync, capture timer is loaded with value in phase register.