Module esp32c6::spi1::cache_fctrl

SPI1 bit mode control register.

Structs

• CACHE_FCTRL_SPEC
  SPI1 bit mode control register.

Type Aliases

• CACHE_USR_ADDR_4BYTE_R
  Field CACHE_USR_ADDR_4BYTE reader - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
• CACHE_USR_ADDR_4BYTE_W
  Field CACHE_USR_ADDR_4BYTE writer - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
• FADDR_DUAL_R
  Field FADDR_DUAL reader - For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
• FADDR_DUAL_W
  Field FADDR_DUAL writer - For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
• FADDR_QUAD_R
  Field FADDR_QUAD reader - For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
• FADDR_QUAD_W
  Field FADDR_QUAD writer - For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
• FDIN_DUAL_R
  Field FDIN_DUAL reader - For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
• FDIN_DUAL_W
  Field FDIN_DUAL writer - For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
• FDIN_QUAD_R
  Field FDIN_QUAD reader - For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
• FDIN_QUAD_W
  Field FDIN_QUAD writer - For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
• FDOUT_DUAL_R
  Field FDOUT_DUAL reader - For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
• FDOUT_DUAL_W
  Field FDOUT_DUAL writer - For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
• FDOUT_QUAD_R
  Field FDOUT_QUAD reader - For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
• FDOUT_QUAD_W
  Field FDOUT_QUAD writer - For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
• R
  Register CACHE_FCTRL reader
• W
  Register CACHE_FCTRL writer