Type Alias esp32c6::extmem::cache_sync_ctrl::W

source ·
pub type W = W<CACHE_SYNC_CTRL_SPEC>;
Expand description

Register CACHE_SYNC_CTRL writer

Aliased Type§

struct W { /* private fields */ }

Implementations§

source§

impl W

source

pub fn cache_invalidate_ena( &mut self ) -> CACHE_INVALIDATE_ENA_W<'_, CACHE_SYNC_CTRL_SPEC>

Bit 0 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. Note that this bit and the other sync-bits (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time.

source

pub fn cache_clean_ena(&mut self) -> CACHE_CLEAN_ENA_W<'_, CACHE_SYNC_CTRL_SPEC>

Bit 1 - The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. Note that this bit and the other sync-bits (invalidate_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time.

source

pub fn cache_writeback_ena( &mut self ) -> CACHE_WRITEBACK_ENA_W<'_, CACHE_SYNC_CTRL_SPEC>

Bit 2 - The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time.

source

pub fn cache_writeback_invalidate_ena( &mut self ) -> CACHE_WRITEBACK_INVALIDATE_ENA_W<'_, CACHE_SYNC_CTRL_SPEC>

Bit 3 - The bit is used to enable writeback-invalidate operation. It will be cleared by hardware after writeback-invalidate operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time.

source

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

§Safety

Passing incorrect value can cause undefined behaviour. See reference manual