Type Alias esp32c6::ledc::int_st::R

pub type R = R<INT_ST_SPEC>;

Register INT_ST reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn timer0_ovf_int_st(&self) -> TIMER0_OVF_INT_ST_R

Bit 0 - This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1.

pub fn timer1_ovf_int_st(&self) -> TIMER1_OVF_INT_ST_R

Bit 1 - This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1.

pub fn timer2_ovf_int_st(&self) -> TIMER2_OVF_INT_ST_R

Bit 2 - This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1.

pub fn timer3_ovf_int_st(&self) -> TIMER3_OVF_INT_ST_R

Bit 3 - This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1.

pub fn duty_chng_end_ch0_int_st(&self) -> DUTY_CHNG_END_CH0_INT_ST_R

Bit 4 - This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1.

pub fn duty_chng_end_ch1_int_st(&self) -> DUTY_CHNG_END_CH1_INT_ST_R

Bit 5 - This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1.

pub fn duty_chng_end_ch2_int_st(&self) -> DUTY_CHNG_END_CH2_INT_ST_R

Bit 6 - This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1.

pub fn duty_chng_end_ch3_int_st(&self) -> DUTY_CHNG_END_CH3_INT_ST_R

Bit 7 - This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1.

pub fn duty_chng_end_ch4_int_st(&self) -> DUTY_CHNG_END_CH4_INT_ST_R

Bit 8 - This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1.

pub fn duty_chng_end_ch5_int_st(&self) -> DUTY_CHNG_END_CH5_INT_ST_R

Bit 9 - This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1.

pub fn ovf_cnt_ch0_int_st(&self) -> OVF_CNT_CH0_INT_ST_R

Bit 12 - This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1.

pub fn ovf_cnt_ch1_int_st(&self) -> OVF_CNT_CH1_INT_ST_R

Bit 13 - This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1.

pub fn ovf_cnt_ch2_int_st(&self) -> OVF_CNT_CH2_INT_ST_R

Bit 14 - This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1.

pub fn ovf_cnt_ch3_int_st(&self) -> OVF_CNT_CH3_INT_ST_R

Bit 15 - This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1.

pub fn ovf_cnt_ch4_int_st(&self) -> OVF_CNT_CH4_INT_ST_R

Bit 16 - This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1.

pub fn ovf_cnt_ch5_int_st(&self) -> OVF_CNT_CH5_INT_ST_R

Bit 17 - This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1.