Type Alias esp32c6::hinf::cfg_data1::R

pub type R = R<CFG_DATA1_SPEC>;

Register CFG_DATA1 reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn sdio_enable(&self) -> SDIO_ENABLE_R

Bit 0 - Sdio clock enable

pub fn sdio_ioready1(&self) -> SDIO_IOREADY1_R

Bit 1 - sdio function1 io ready signal in cis

pub fn highspeed_enable(&self) -> HIGHSPEED_ENABLE_R

Bit 2 - Highspeed enable in cccr

pub fn highspeed_mode(&self) -> HIGHSPEED_MODE_R

Bit 3 - highspeed mode status in cccr

pub fn sdio_cd_enable(&self) -> SDIO_CD_ENABLE_R

Bit 4 - sdio card detect enable

pub fn sdio_ioready2(&self) -> SDIO_IOREADY2_R

Bit 5 - sdio function1 io ready signal in cis

pub fn sdio_int_mask(&self) -> SDIO_INT_MASK_R

Bit 6 - mask sdio interrupt in cccr, high active

pub fn ioenable2(&self) -> IOENABLE2_R

Bit 7 - ioe2 status in cccr

pub fn cd_disable(&self) -> CD_DISABLE_R

Bit 8 - card disable status in cccr

pub fn func1_eps(&self) -> FUNC1_EPS_R

Bit 9 - function1 eps status in fbr

pub fn emp(&self) -> EMP_R

Bit 10 - empc status in cccr

pub fn ioenable1(&self) -> IOENABLE1_R

Bit 11 - ioe1 status in cccr

pub fn sdio_ver(&self) -> SDIO_VER_R

Bits 12:23 - sdio version in cccr

pub fn func2_eps(&self) -> FUNC2_EPS_R

Bit 24 - function2 eps status in fbr

pub fn sdio20_conf(&self) -> SDIO20_CONF_R

Bits 25:31 - 29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat in delayed cycles control,0:no delay, 1:delay 1 cycle. [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed mode. [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when [12]=0,posedge when highspeed mode enable. [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay. [28]: sdio data pad pull up enable