Struct esp32c6::mcpwm0::RegisterBlock

#[repr(C)]
pub struct RegisterBlock { /* private fields */ }

Register block

Implementations

impl RegisterBlock

pub const fn clk_cfg(&self) -> &CLK_CFG

0x00 - PWM clock prescaler register.

pub const fn timer0_cfg0(&self) -> &TIMER0_CFG0

0x04 - PWM timer0 period and update method configuration register.

pub const fn timer0_cfg1(&self) -> &TIMER0_CFG1

0x08 - PWM timer0 working mode and start/stop control configuration register.

pub const fn timer0_sync(&self) -> &TIMER0_SYNC

0x0c - PWM timer0 sync function configuration register.

pub const fn timer0_status(&self) -> &TIMER0_STATUS

0x10 - PWM timer0 status register.

pub const fn timer1_cfg0(&self) -> &TIMER1_CFG0

0x14 - PWM timer1 period and update method configuration register.

pub const fn timer1_cfg1(&self) -> &TIMER1_CFG1

0x18 - PWM timer1 working mode and start/stop control configuration register.

pub const fn timer1_sync(&self) -> &TIMER1_SYNC

0x1c - PWM timer1 sync function configuration register.

pub const fn timer1_status(&self) -> &TIMER1_STATUS

0x20 - PWM timer1 status register.

pub const fn timer2_cfg0(&self) -> &TIMER2_CFG0

0x24 - PWM timer2 period and update method configuration register.

pub const fn timer2_cfg1(&self) -> &TIMER2_CFG1

0x28 - PWM timer2 working mode and start/stop control configuration register.

pub const fn timer2_sync(&self) -> &TIMER2_SYNC

0x2c - PWM timer2 sync function configuration register.

pub const fn timer2_status(&self) -> &TIMER2_STATUS

0x30 - PWM timer2 status register.

pub const fn timer_synci_cfg(&self) -> &TIMER_SYNCI_CFG

0x34 - Synchronization input selection for three PWM timers.

pub const fn operator_timersel(&self) -> &OPERATOR_TIMERSEL

0x38 - Select specific timer for PWM operators.

pub const fn gen0_stmp_cfg(&self) -> &GEN0_STMP_CFG

0x3c - Transfer status and update method for time stamp registers A and B

pub const fn gen0_tstmp_a(&self) -> &GEN0_TSTMP_A

0x40 - Shadow register for register A.

pub const fn gen0_tstmp_b(&self) -> &GEN0_TSTMP_B

0x44 - Shadow register for register B.

pub const fn gen0_cfg0(&self) -> &GEN0_CFG0

0x48 - Fault event T0 and T1 handling

pub const fn gen0_force(&self) -> &GEN0_FORCE

0x4c - Permissives to force PWM0A and PWM0B outputs by software

pub const fn gen0_a(&self) -> &GEN0_A

0x50 - Actions triggered by events on PWM0A

pub const fn gen0_b(&self) -> &GEN0_B

0x54 - Actions triggered by events on PWM0B

pub const fn dt0_cfg(&self) -> &DT0_CFG

0x58 - dead time type selection and configuration

pub const fn dt0_fed_cfg(&self) -> &DT0_FED_CFG

0x5c - Shadow register for falling edge delay (FED).

pub const fn dt0_red_cfg(&self) -> &DT0_RED_CFG

0x60 - Shadow register for rising edge delay (RED).

pub const fn carrier0_cfg(&self) -> &CARRIER0_CFG

0x64 - Carrier enable and configuratoin

pub const fn fh0_cfg0(&self) -> &FH0_CFG0

0x68 - Actions on PWM0A and PWM0B trip events

pub const fn fh0_cfg1(&self) -> &FH0_CFG1

0x6c - Software triggers for fault handler actions

pub const fn fh0_status(&self) -> &FH0_STATUS

0x70 - Status of fault events.

pub const fn gen1_stmp_cfg(&self) -> &GEN1_STMP_CFG

0x74 - Transfer status and update method for time stamp registers A and B

pub const fn gen1_tstmp_a(&self) -> &GEN1_TSTMP_A

0x78 - Shadow register for register A.

pub const fn gen1_tstmp_b(&self) -> &GEN1_TSTMP_B

0x7c - Shadow register for register B.

pub const fn gen1_cfg0(&self) -> &GEN1_CFG0

0x80 - Fault event T0 and T1 handling

pub const fn gen1_force(&self) -> &GEN1_FORCE

0x84 - Permissives to force PWM1A and PWM1B outputs by software

pub const fn gen1_a(&self) -> &GEN1_A

0x88 - Actions triggered by events on PWM1A

pub const fn gen1_b(&self) -> &GEN1_B

0x8c - Actions triggered by events on PWM1B

pub const fn dt1_cfg(&self) -> &DT1_CFG

0x90 - dead time type selection and configuration

pub const fn dt1_fed_cfg(&self) -> &DT1_FED_CFG

0x94 - Shadow register for falling edge delay (FED).

pub const fn dt1_red_cfg(&self) -> &DT1_RED_CFG

0x98 - Shadow register for rising edge delay (RED).

pub const fn carrier1_cfg(&self) -> &CARRIER1_CFG

0x9c - Carrier enable and configuratoin

pub const fn fh1_cfg0(&self) -> &FH1_CFG0

0xa0 - Actions on PWM1A and PWM1B trip events

pub const fn fh1_cfg1(&self) -> &FH1_CFG1

0xa4 - Software triggers for fault handler actions

pub const fn fh1_status(&self) -> &FH1_STATUS

0xa8 - Status of fault events.

pub const fn gen2_stmp_cfg(&self) -> &GEN2_STMP_CFG

0xac - Transfer status and update method for time stamp registers A and B

pub const fn gen2_tstmp_a(&self) -> &GEN2_TSTMP_A

0xb0 - Shadow register for register A.

pub const fn gen2_tstmp_b(&self) -> &GEN2_TSTMP_B

0xb4 - Shadow register for register B.

pub const fn gen2_cfg0(&self) -> &GEN2_CFG0

0xb8 - Fault event T0 and T1 handling

pub const fn gen2_force(&self) -> &GEN2_FORCE

0xbc - Permissives to force PWM2A and PWM2B outputs by software

pub const fn gen2_a(&self) -> &GEN2_A

0xc0 - Actions triggered by events on PWM2A

pub const fn gen2_b(&self) -> &GEN2_B

0xc4 - Actions triggered by events on PWM2B

pub const fn dt2_cfg(&self) -> &DT2_CFG

0xc8 - dead time type selection and configuration

pub const fn dt2_fed_cfg(&self) -> &DT2_FED_CFG

0xcc - Shadow register for falling edge delay (FED).

pub const fn dt2_red_cfg(&self) -> &DT2_RED_CFG

0xd0 - Shadow register for rising edge delay (RED).

pub const fn carrier2_cfg(&self) -> &CARRIER2_CFG

0xd4 - Carrier enable and configuratoin

pub const fn fh2_cfg0(&self) -> &FH2_CFG0

0xd8 - Actions on PWM2A and PWM2B trip events

pub const fn fh2_cfg1(&self) -> &FH2_CFG1

0xdc - Software triggers for fault handler actions

pub const fn fh2_status(&self) -> &FH2_STATUS

0xe0 - Status of fault events.

pub const fn fault_detect(&self) -> &FAULT_DETECT

0xe4 - Fault detection configuration and status

pub const fn cap_timer_cfg(&self) -> &CAP_TIMER_CFG

0xe8 - Configure capture timer

pub const fn cap_timer_phase(&self) -> &CAP_TIMER_PHASE

0xec - Phase for capture timer sync

pub const fn cap_ch0_cfg(&self) -> &CAP_CH0_CFG

0xf0 - Capture channel 0 configuration and enable

pub const fn cap_ch1_cfg(&self) -> &CAP_CH1_CFG

0xf4 - Capture channel 1 configuration and enable

pub const fn cap_ch2_cfg(&self) -> &CAP_CH2_CFG

0xf8 - Capture channel 2 configuration and enable

pub const fn cap_ch0(&self) -> &CAP_CH0

0xfc - ch0 capture value status register

pub const fn cap_ch1(&self) -> &CAP_CH1

0x100 - ch1 capture value status register

pub const fn cap_ch2(&self) -> &CAP_CH2

0x104 - ch2 capture value status register

pub const fn cap_status(&self) -> &CAP_STATUS

0x108 - Edge of last capture trigger

pub const fn update_cfg(&self) -> &UPDATE_CFG

0x10c - Enable update.

pub const fn int_ena(&self) -> &INT_ENA

0x110 - Interrupt enable bits

pub const fn int_raw(&self) -> &INT_RAW

0x114 - Raw interrupt status

pub const fn int_st(&self) -> &INT_ST

0x118 - Masked interrupt status

pub const fn int_clr(&self) -> &INT_CLR

0x11c - Interrupt clear bits

pub const fn evt_en(&self) -> &EVT_EN

0x120 - MCPWM event enable register

pub const fn task_en(&self) -> &TASK_EN

0x124 - MCPWM task enable register

pub const fn clk(&self) -> &CLK

0x128 - MCPWM APB configuration register

pub const fn version(&self) -> &VERSION

0x12c - Version register.