Type Alias esp32c6::spi2::din_num::R

pub type R = R<DIN_NUM_SPEC>;

Register DIN_NUM reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn din0_num(&self) -> DIN0_NUM_R

Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.

pub fn din1_num(&self) -> DIN1_NUM_R

Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.

pub fn din2_num(&self) -> DIN2_NUM_R

Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.

pub fn din3_num(&self) -> DIN3_NUM_R

Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.

pub fn din4_num(&self) -> DIN4_NUM_R

Bits 8:9 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.

pub fn din5_num(&self) -> DIN5_NUM_R

Bits 10:11 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.

pub fn din6_num(&self) -> DIN6_NUM_R

Bits 12:13 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.

pub fn din7_num(&self) -> DIN7_NUM_R

Bits 14:15 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.