Struct esp32c6::extmem::level_split1::LEVEL_SPLIT1_SPEC

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pub struct LEVEL_SPLIT1_SPEC;
Expand description

USED TO SPLIT L1 CACHE AND L2 CACHE

You can read this register and get level_split1::R. See API.

Trait Implementations§

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impl RegisterSpec for LEVEL_SPLIT1_SPEC

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type Ux = u32

Raw register type (u8, u16, u32, …).
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impl Resettable for LEVEL_SPLIT1_SPEC

reset() method sets LEVEL_SPLIT1 to value 0x03a8

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const RESET_VALUE: Self::Ux = {transmute(0x000003a8): <extmem::level_split1::LEVEL_SPLIT1_SPEC as generic::RegisterSpec>::Ux}

Reset value of the register.
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fn reset_value() -> Self::Ux

Reset value of the register.
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impl Readable for LEVEL_SPLIT1_SPEC

read() method returns level_split1::R reader structure

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