Type Alias esp32c6::spi0::spi_mem_ctrl::R

pub type R = R<SPI_MEM_CTRL_SPEC>;

Register SPI_MEM_CTRL reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn spi_mem_wdummy_dqs_always_out(&self) -> SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_R

Bit 0 - In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller.

pub fn spi_mem_wdummy_always_out(&self) -> SPI_MEM_WDUMMY_ALWAYS_OUT_R

Bit 1 - In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller.

pub fn spi_mem_fdummy_rin(&self) -> SPI_MEM_FDUMMY_RIN_R

Bit 2 - In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase.

pub fn spi_mem_fdummy_wout(&self) -> SPI_MEM_FDUMMY_WOUT_R

Bit 3 - In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash.

pub fn spi_mem_fdout_oct(&self) -> SPI_MEM_FDOUT_OCT_R

Bit 4 - Apply 8 signals during write-data phase 1:enable 0: disable

pub fn spi_mem_fdin_oct(&self) -> SPI_MEM_FDIN_OCT_R

Bit 5 - Apply 8 signals during read-data phase 1:enable 0: disable

pub fn spi_mem_faddr_oct(&self) -> SPI_MEM_FADDR_OCT_R

Bit 6 - Apply 8 signals during address phase 1:enable 0: disable

pub fn spi_mem_fcmd_quad(&self) -> SPI_MEM_FCMD_QUAD_R

Bit 8 - Apply 4 signals during command phase 1:enable 0: disable

pub fn spi_mem_fcmd_oct(&self) -> SPI_MEM_FCMD_OCT_R

Bit 9 - Apply 8 signals during command phase 1:enable 0: disable

pub fn spi_mem_fastrd_mode(&self) -> SPI_MEM_FASTRD_MODE_R

Bit 13 - This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable.

pub fn spi_mem_fread_dual(&self) -> SPI_MEM_FREAD_DUAL_R

Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.

pub fn spi_mem_q_pol(&self) -> SPI_MEM_Q_POL_R

Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low

pub fn spi_mem_d_pol(&self) -> SPI_MEM_D_POL_R

Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low

pub fn spi_mem_fread_quad(&self) -> SPI_MEM_FREAD_QUAD_R

Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable.

pub fn spi_mem_wp(&self) -> SPI_MEM_WP_R

Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low.

pub fn spi_mem_fread_dio(&self) -> SPI_MEM_FREAD_DIO_R

Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.

pub fn spi_mem_fread_qio(&self) -> SPI_MEM_FREAD_QIO_R

Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.

pub fn spi_mem_dqs_ie_always_on(&self) -> SPI_MEM_DQS_IE_ALWAYS_ON_R

Bit 30 - When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.

pub fn spi_mem_data_ie_always_on(&self) -> SPI_MEM_DATA_IE_ALWAYS_ON_R

Bit 31 - When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.