Module esp32c6::dma

DMA (Direct Memory Access) Controller

Modules

• ahb_test
  reserved
• date
  Version control register
• in_conf0_ch
  Configure 0 register of Rx channel 0
• in_conf1_ch
  Configure 1 register of Rx channel 0
• in_dscr_bf0_ch
  The last inlink descriptor address of Rx channel 0
• in_dscr_bf1_ch
  The second-to-last inlink descriptor address of Rx channel 0
• in_dscr_ch
  Current inlink descriptor address of Rx channel 0
• in_err_eof_des_addr_ch
  Inlink descriptor address when errors occur of Rx channel 0
• in_int_clr_ch
  Interrupt clear bits of channel 0
• in_int_ena_ch
  Interrupt enable bits of channel 0
• in_int_raw_ch
  Raw status interrupt of channel 0
• in_int_st_ch
  Masked interrupt of channel 0
• in_link_ch
  Link descriptor configure and control register of Rx channel 0
• in_peri_sel_ch
  Peripheral selection of Rx channel 0
• in_pop_ch
  Pop control register of Rx channel 0
• in_pri_ch
  Priority register of Rx channel 0
• in_state_ch
  Receive status of Rx channel 0
• in_suc_eof_des_addr_ch
  Inlink descriptor address when EOF occurs of Rx channel 0
• infifo_status_ch
  Receive FIFO status of Rx channel 0
• misc_conf
  MISC register
• out_conf0_ch
  Configure 0 register of Tx channel 1
• out_conf1_ch
  Configure 1 register of Tx channel 0
• out_dscr_bf0_ch
  The last inlink descriptor address of Tx channel 0
• out_dscr_bf1_ch
  The second-to-last inlink descriptor address of Tx channel 0
• out_dscr_ch
  Current inlink descriptor address of Tx channel 0
• out_eof_bfr_des_addr_ch
  The last outlink descriptor address when EOF occurs of Tx channel 0
• out_eof_des_addr_ch
  Outlink descriptor address when EOF occurs of Tx channel 0
• out_int_clr_ch
  Interrupt clear bits of channel 0
• out_int_ena_ch
  Interrupt enable bits of channel 0
• out_int_raw_ch
  Raw status interrupt of channel 0
• out_int_st_ch
  Masked interrupt of channel 0
• out_link_ch
  Link descriptor configure and control register of Tx channel 0
• out_peri_sel_ch
  Peripheral selection of Tx channel 0
• out_pri_ch
  Priority register of Tx channel 0.
• out_push_ch
  Push control register of Rx channel 0
• out_state_ch
  Transmit status of Tx channel 0
• outfifo_status_ch
  Transmit FIFO status of Tx channel 0

Structs

• RegisterBlock
  Register block

Type Aliases

• AHB_TEST
  AHB_TEST (rw) register accessor: reserved
• DATE
  DATE (rw) register accessor: Version control register
• INFIFO_STATUS_CH
  INFIFO_STATUS_CH (r) register accessor: Receive FIFO status of Rx channel 0
• IN_CONF0_CH
  IN_CONF0_CH (rw) register accessor: Configure 0 register of Rx channel 0
• IN_CONF1_CH
  IN_CONF1_CH (rw) register accessor: Configure 1 register of Rx channel 0
• IN_DSCR_BF0_CH
  IN_DSCR_BF0_CH (r) register accessor: The last inlink descriptor address of Rx channel 0
• IN_DSCR_BF1_CH
  IN_DSCR_BF1_CH (r) register accessor: The second-to-last inlink descriptor address of Rx channel 0
• IN_DSCR_CH
  IN_DSCR_CH (r) register accessor: Current inlink descriptor address of Rx channel 0
• IN_ERR_EOF_DES_ADDR_CH
  IN_ERR_EOF_DES_ADDR_CH (r) register accessor: Inlink descriptor address when errors occur of Rx channel 0
• IN_INT_CLR_CH
  IN_INT_CLR_CH (w) register accessor: Interrupt clear bits of channel 0
• IN_INT_ENA_CH
  IN_INT_ENA_CH (rw) register accessor: Interrupt enable bits of channel 0
• IN_INT_RAW_CH
  IN_INT_RAW_CH (rw) register accessor: Raw status interrupt of channel 0
• IN_INT_ST_CH
  IN_INT_ST_CH (r) register accessor: Masked interrupt of channel 0
• IN_LINK_CH
  IN_LINK_CH (rw) register accessor: Link descriptor configure and control register of Rx channel 0
• IN_PERI_SEL_CH
  IN_PERI_SEL_CH (rw) register accessor: Peripheral selection of Rx channel 0
• IN_POP_CH
  IN_POP_CH (rw) register accessor: Pop control register of Rx channel 0
• IN_PRI_CH
  IN_PRI_CH (rw) register accessor: Priority register of Rx channel 0
• IN_STATE_CH
  IN_STATE_CH (r) register accessor: Receive status of Rx channel 0
• IN_SUC_EOF_DES_ADDR_CH
  IN_SUC_EOF_DES_ADDR_CH (r) register accessor: Inlink descriptor address when EOF occurs of Rx channel 0
• MISC_CONF
  MISC_CONF (rw) register accessor: MISC register
• OUTFIFO_STATUS_CH
  OUTFIFO_STATUS_CH (r) register accessor: Transmit FIFO status of Tx channel 0
• OUT_CONF0_CH
  OUT_CONF0_CH (rw) register accessor: Configure 0 register of Tx channel 1
• OUT_CONF1_CH
  OUT_CONF1_CH (rw) register accessor: Configure 1 register of Tx channel 0
• OUT_DSCR_BF0_CH
  OUT_DSCR_BF0_CH (r) register accessor: The last inlink descriptor address of Tx channel 0
• OUT_DSCR_BF1_CH
  OUT_DSCR_BF1_CH (r) register accessor: The second-to-last inlink descriptor address of Tx channel 0
• OUT_DSCR_CH
  OUT_DSCR_CH (r) register accessor: Current inlink descriptor address of Tx channel 0
• OUT_EOF_BFR_DES_ADDR_CH
  OUT_EOF_BFR_DES_ADDR_CH (r) register accessor: The last outlink descriptor address when EOF occurs of Tx channel 0
• OUT_EOF_DES_ADDR_CH
  OUT_EOF_DES_ADDR_CH (r) register accessor: Outlink descriptor address when EOF occurs of Tx channel 0
• OUT_INT_CLR_CH
  OUT_INT_CLR_CH (w) register accessor: Interrupt clear bits of channel 0
• OUT_INT_ENA_CH
  OUT_INT_ENA_CH (rw) register accessor: Interrupt enable bits of channel 0
• OUT_INT_RAW_CH
  OUT_INT_RAW_CH (rw) register accessor: Raw status interrupt of channel 0
• OUT_INT_ST_CH
  OUT_INT_ST_CH (r) register accessor: Masked interrupt of channel 0
• OUT_LINK_CH
  OUT_LINK_CH (rw) register accessor: Link descriptor configure and control register of Tx channel 0
• OUT_PERI_SEL_CH
  OUT_PERI_SEL_CH (rw) register accessor: Peripheral selection of Tx channel 0
• OUT_PRI_CH
  OUT_PRI_CH (rw) register accessor: Priority register of Tx channel 0.
• OUT_PUSH_CH
  OUT_PUSH_CH (rw) register accessor: Push control register of Rx channel 0
• OUT_STATE_CH
  OUT_STATE_CH (r) register accessor: Transmit status of Tx channel 0