Module esp32c6::dma::in_conf0_ch
source · Expand description
Configure 0 register of Rx channel 0
Structs
- Configure 0 register of Rx channel 0
Type Aliases
- Field
INDSCR_BURST_EN
reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. - Field
INDSCR_BURST_EN
writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. - Field
IN_DATA_BURST_EN
reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. - Field
IN_DATA_BURST_EN
writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. - Field
IN_ETM_EN
reader - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task. - Field
IN_ETM_EN
writer - Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task. - Field
IN_LOOP_TEST
reader - reserved - Field
IN_LOOP_TEST
writer - reserved - Field
IN_RST
reader - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. - Field
IN_RST
writer - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. - Field
MEM_TRANS_EN
reader - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. - Field
MEM_TRANS_EN
writer - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. - Register
IN_CONF0_CH%s
reader - Register
IN_CONF0_CH%s
writer