Expand description
Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller
Modules§
- afifo_
status - UART AFIFO Status
- at_
cmd_ char_ sync - AT escape sequence detection configuration
- at_
cmd_ gaptout_ sync - Timeout configuration
- at_
cmd_ postcnt_ sync - Post-sequence timing configuration
- at_
cmd_ precnt_ sync - Pre-sequence timing configuration
- clk_
conf - UART core clock configuration
- clkdiv_
sync - Clock divider configuration
- conf0_
sync - Configuration register 0
- conf1
- Configuration register 1
- date
- UART Version register
- fifo
- FIFO data register
- fsm_
status - UART transmit and receive status.
- hwfc_
conf_ sync - Hardware flow-control configuration
- id
- UART ID register
- idle_
conf_ sync - Frame-end idle configuration
- int_clr
- Interrupt clear bits
- int_ena
- Interrupt enable bits
- int_raw
- Raw interrupt status
- int_st
- Masked interrupt status
- mem_
conf - UART memory power configuration
- mem_
rx_ status - Rx-SRAM write and read offset address.
- mem_
tx_ status - Tx-SRAM write and read offset address.
- reg_
update - UART Registers Configuration Update register
- rs485_
conf_ sync - RS485 mode configuration
- rx_filt
- Rx Filter configuration
- sleep_
conf0 - UART sleep configure register 0
- sleep_
conf1 - UART sleep configure register 1
- sleep_
conf2 - UART sleep configure register 2
- status
- UART status register
- swfc_
conf0_ sync - Software flow-control character configuration
- swfc_
conf1 - Software flow-control character configuration
- tout_
conf_ sync - UART threshold and allocation configuration
- txbrk_
conf_ sync - Tx Break character configuration
Structs§
- Register
Block - Register block
Type Aliases§
- AFIFO_
STATUS - AFIFO_STATUS (r) register accessor: UART AFIFO Status
- AT_
CMD_ CHAR_ SYNC - AT_CMD_CHAR_SYNC (rw) register accessor: AT escape sequence detection configuration
- AT_
CMD_ GAPTOUT_ SYNC - AT_CMD_GAPTOUT_SYNC (rw) register accessor: Timeout configuration
- AT_
CMD_ POSTCNT_ SYNC - AT_CMD_POSTCNT_SYNC (rw) register accessor: Post-sequence timing configuration
- AT_
CMD_ PRECNT_ SYNC - AT_CMD_PRECNT_SYNC (rw) register accessor: Pre-sequence timing configuration
- CLKDIV_
SYNC - CLKDIV_SYNC (rw) register accessor: Clock divider configuration
- CLK_
CONF - CLK_CONF (rw) register accessor: UART core clock configuration
- CONF0_
SYNC - CONF0_SYNC (rw) register accessor: Configuration register 0
- CONF1
- CONF1 (rw) register accessor: Configuration register 1
- DATE
- DATE (rw) register accessor: UART Version register
- FIFO
- FIFO (rw) register accessor: FIFO data register
- FSM_
STATUS - FSM_STATUS (r) register accessor: UART transmit and receive status.
- HWFC_
CONF_ SYNC - HWFC_CONF_SYNC (rw) register accessor: Hardware flow-control configuration
- ID
- ID (rw) register accessor: UART ID register
- IDLE_
CONF_ SYNC - IDLE_CONF_SYNC (rw) register accessor: Frame-end idle configuration
- INT_CLR
- INT_CLR (w) register accessor: Interrupt clear bits
- INT_ENA
- INT_ENA (rw) register accessor: Interrupt enable bits
- INT_RAW
- INT_RAW (rw) register accessor: Raw interrupt status
- INT_ST
- INT_ST (r) register accessor: Masked interrupt status
- MEM_
CONF - MEM_CONF (rw) register accessor: UART memory power configuration
- MEM_
RX_ STATUS - MEM_RX_STATUS (r) register accessor: Rx-SRAM write and read offset address.
- MEM_
TX_ STATUS - MEM_TX_STATUS (r) register accessor: Tx-SRAM write and read offset address.
- REG_
UPDATE - REG_UPDATE (rw) register accessor: UART Registers Configuration Update register
- RS485_
CONF_ SYNC - RS485_CONF_SYNC (rw) register accessor: RS485 mode configuration
- RX_FILT
- RX_FILT (rw) register accessor: Rx Filter configuration
- SLEEP_
CONF0 - SLEEP_CONF0 (rw) register accessor: UART sleep configure register 0
- SLEEP_
CONF1 - SLEEP_CONF1 (rw) register accessor: UART sleep configure register 1
- SLEEP_
CONF2 - SLEEP_CONF2 (rw) register accessor: UART sleep configure register 2
- STATUS
- STATUS (r) register accessor: UART status register
- SWFC_
CONF0_ SYNC - SWFC_CONF0_SYNC (rw) register accessor: Software flow-control character configuration
- SWFC_
CONF1 - SWFC_CONF1 (rw) register accessor: Software flow-control character configuration
- TOUT_
CONF_ SYNC - TOUT_CONF_SYNC (rw) register accessor: UART threshold and allocation configuration
- TXBRK_
CONF_ SYNC - TXBRK_CONF_SYNC (rw) register accessor: Tx Break character configuration