1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 fifo: FIFO,
6 int_raw: INT_RAW,
7 int_st: INT_ST,
8 int_ena: INT_ENA,
9 int_clr: INT_CLR,
10 clkdiv_sync: CLKDIV_SYNC,
11 rx_filt: RX_FILT,
12 status: STATUS,
13 conf0_sync: CONF0_SYNC,
14 conf1: CONF1,
15 _reserved10: [u8; 0x04],
16 hwfc_conf_sync: HWFC_CONF_SYNC,
17 sleep_conf0: SLEEP_CONF0,
18 sleep_conf1: SLEEP_CONF1,
19 sleep_conf2: SLEEP_CONF2,
20 swfc_conf0_sync: SWFC_CONF0_SYNC,
21 swfc_conf1: SWFC_CONF1,
22 txbrk_conf_sync: TXBRK_CONF_SYNC,
23 idle_conf_sync: IDLE_CONF_SYNC,
24 rs485_conf_sync: RS485_CONF_SYNC,
25 at_cmd_precnt_sync: AT_CMD_PRECNT_SYNC,
26 at_cmd_postcnt_sync: AT_CMD_POSTCNT_SYNC,
27 at_cmd_gaptout_sync: AT_CMD_GAPTOUT_SYNC,
28 at_cmd_char_sync: AT_CMD_CHAR_SYNC,
29 mem_conf: MEM_CONF,
30 tout_conf_sync: TOUT_CONF_SYNC,
31 mem_tx_status: MEM_TX_STATUS,
32 mem_rx_status: MEM_RX_STATUS,
33 fsm_status: FSM_STATUS,
34 _reserved28: [u8; 0x14],
35 clk_conf: CLK_CONF,
36 date: DATE,
37 afifo_status: AFIFO_STATUS,
38 _reserved31: [u8; 0x04],
39 reg_update: REG_UPDATE,
40 id: ID,
41}
42impl RegisterBlock {
43 #[doc = "0x00 - FIFO data register"]
44 #[inline(always)]
45 pub const fn fifo(&self) -> &FIFO {
46 &self.fifo
47 }
48 #[doc = "0x04 - Raw interrupt status"]
49 #[inline(always)]
50 pub const fn int_raw(&self) -> &INT_RAW {
51 &self.int_raw
52 }
53 #[doc = "0x08 - Masked interrupt status"]
54 #[inline(always)]
55 pub const fn int_st(&self) -> &INT_ST {
56 &self.int_st
57 }
58 #[doc = "0x0c - Interrupt enable bits"]
59 #[inline(always)]
60 pub const fn int_ena(&self) -> &INT_ENA {
61 &self.int_ena
62 }
63 #[doc = "0x10 - Interrupt clear bits"]
64 #[inline(always)]
65 pub const fn int_clr(&self) -> &INT_CLR {
66 &self.int_clr
67 }
68 #[doc = "0x14 - Clock divider configuration"]
69 #[inline(always)]
70 pub const fn clkdiv_sync(&self) -> &CLKDIV_SYNC {
71 &self.clkdiv_sync
72 }
73 #[doc = "0x18 - Rx Filter configuration"]
74 #[inline(always)]
75 pub const fn rx_filt(&self) -> &RX_FILT {
76 &self.rx_filt
77 }
78 #[doc = "0x1c - UART status register"]
79 #[inline(always)]
80 pub const fn status(&self) -> &STATUS {
81 &self.status
82 }
83 #[doc = "0x20 - Configuration register 0"]
84 #[inline(always)]
85 pub const fn conf0_sync(&self) -> &CONF0_SYNC {
86 &self.conf0_sync
87 }
88 #[doc = "0x24 - Configuration register 1"]
89 #[inline(always)]
90 pub const fn conf1(&self) -> &CONF1 {
91 &self.conf1
92 }
93 #[doc = "0x2c - Hardware flow-control configuration"]
94 #[inline(always)]
95 pub const fn hwfc_conf_sync(&self) -> &HWFC_CONF_SYNC {
96 &self.hwfc_conf_sync
97 }
98 #[doc = "0x30 - UART sleep configure register 0"]
99 #[inline(always)]
100 pub const fn sleep_conf0(&self) -> &SLEEP_CONF0 {
101 &self.sleep_conf0
102 }
103 #[doc = "0x34 - UART sleep configure register 1"]
104 #[inline(always)]
105 pub const fn sleep_conf1(&self) -> &SLEEP_CONF1 {
106 &self.sleep_conf1
107 }
108 #[doc = "0x38 - UART sleep configure register 2"]
109 #[inline(always)]
110 pub const fn sleep_conf2(&self) -> &SLEEP_CONF2 {
111 &self.sleep_conf2
112 }
113 #[doc = "0x3c - Software flow-control character configuration"]
114 #[inline(always)]
115 pub const fn swfc_conf0_sync(&self) -> &SWFC_CONF0_SYNC {
116 &self.swfc_conf0_sync
117 }
118 #[doc = "0x40 - Software flow-control character configuration"]
119 #[inline(always)]
120 pub const fn swfc_conf1(&self) -> &SWFC_CONF1 {
121 &self.swfc_conf1
122 }
123 #[doc = "0x44 - Tx Break character configuration"]
124 #[inline(always)]
125 pub const fn txbrk_conf_sync(&self) -> &TXBRK_CONF_SYNC {
126 &self.txbrk_conf_sync
127 }
128 #[doc = "0x48 - Frame-end idle configuration"]
129 #[inline(always)]
130 pub const fn idle_conf_sync(&self) -> &IDLE_CONF_SYNC {
131 &self.idle_conf_sync
132 }
133 #[doc = "0x4c - RS485 mode configuration"]
134 #[inline(always)]
135 pub const fn rs485_conf_sync(&self) -> &RS485_CONF_SYNC {
136 &self.rs485_conf_sync
137 }
138 #[doc = "0x50 - Pre-sequence timing configuration"]
139 #[inline(always)]
140 pub const fn at_cmd_precnt_sync(&self) -> &AT_CMD_PRECNT_SYNC {
141 &self.at_cmd_precnt_sync
142 }
143 #[doc = "0x54 - Post-sequence timing configuration"]
144 #[inline(always)]
145 pub const fn at_cmd_postcnt_sync(&self) -> &AT_CMD_POSTCNT_SYNC {
146 &self.at_cmd_postcnt_sync
147 }
148 #[doc = "0x58 - Timeout configuration"]
149 #[inline(always)]
150 pub const fn at_cmd_gaptout_sync(&self) -> &AT_CMD_GAPTOUT_SYNC {
151 &self.at_cmd_gaptout_sync
152 }
153 #[doc = "0x5c - AT escape sequence detection configuration"]
154 #[inline(always)]
155 pub const fn at_cmd_char_sync(&self) -> &AT_CMD_CHAR_SYNC {
156 &self.at_cmd_char_sync
157 }
158 #[doc = "0x60 - UART memory power configuration"]
159 #[inline(always)]
160 pub const fn mem_conf(&self) -> &MEM_CONF {
161 &self.mem_conf
162 }
163 #[doc = "0x64 - UART threshold and allocation configuration"]
164 #[inline(always)]
165 pub const fn tout_conf_sync(&self) -> &TOUT_CONF_SYNC {
166 &self.tout_conf_sync
167 }
168 #[doc = "0x68 - Tx-SRAM write and read offset address."]
169 #[inline(always)]
170 pub const fn mem_tx_status(&self) -> &MEM_TX_STATUS {
171 &self.mem_tx_status
172 }
173 #[doc = "0x6c - Rx-SRAM write and read offset address."]
174 #[inline(always)]
175 pub const fn mem_rx_status(&self) -> &MEM_RX_STATUS {
176 &self.mem_rx_status
177 }
178 #[doc = "0x70 - UART transmit and receive status."]
179 #[inline(always)]
180 pub const fn fsm_status(&self) -> &FSM_STATUS {
181 &self.fsm_status
182 }
183 #[doc = "0x88 - UART core clock configuration"]
184 #[inline(always)]
185 pub const fn clk_conf(&self) -> &CLK_CONF {
186 &self.clk_conf
187 }
188 #[doc = "0x8c - UART Version register"]
189 #[inline(always)]
190 pub const fn date(&self) -> &DATE {
191 &self.date
192 }
193 #[doc = "0x90 - UART AFIFO Status"]
194 #[inline(always)]
195 pub const fn afifo_status(&self) -> &AFIFO_STATUS {
196 &self.afifo_status
197 }
198 #[doc = "0x98 - UART Registers Configuration Update register"]
199 #[inline(always)]
200 pub const fn reg_update(&self) -> ®_UPDATE {
201 &self.reg_update
202 }
203 #[doc = "0x9c - UART ID register"]
204 #[inline(always)]
205 pub const fn id(&self) -> &ID {
206 &self.id
207 }
208}
209#[doc = "FIFO (rw) register accessor: FIFO data register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo`] module"]
210pub type FIFO = crate::Reg<fifo::FIFO_SPEC>;
211#[doc = "FIFO data register"]
212pub mod fifo;
213#[doc = "INT_RAW (rw) register accessor: Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"]
214pub type INT_RAW = crate::Reg<int_raw::INT_RAW_SPEC>;
215#[doc = "Raw interrupt status"]
216pub mod int_raw;
217#[doc = "INT_ST (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"]
218pub type INT_ST = crate::Reg<int_st::INT_ST_SPEC>;
219#[doc = "Masked interrupt status"]
220pub mod int_st;
221#[doc = "INT_ENA (rw) register accessor: Interrupt enable bits\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"]
222pub type INT_ENA = crate::Reg<int_ena::INT_ENA_SPEC>;
223#[doc = "Interrupt enable bits"]
224pub mod int_ena;
225#[doc = "INT_CLR (w) register accessor: Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
226pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
227#[doc = "Interrupt clear bits"]
228pub mod int_clr;
229#[doc = "CLKDIV_SYNC (rw) register accessor: Clock divider configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv_sync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv_sync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv_sync`] module"]
230pub type CLKDIV_SYNC = crate::Reg<clkdiv_sync::CLKDIV_SYNC_SPEC>;
231#[doc = "Clock divider configuration"]
232pub mod clkdiv_sync;
233#[doc = "RX_FILT (rw) register accessor: Rx Filter configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_filt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_filt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_filt`] module"]
234pub type RX_FILT = crate::Reg<rx_filt::RX_FILT_SPEC>;
235#[doc = "Rx Filter configuration"]
236pub mod rx_filt;
237#[doc = "STATUS (r) register accessor: UART status register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"]
238pub type STATUS = crate::Reg<status::STATUS_SPEC>;
239#[doc = "UART status register"]
240pub mod status;
241#[doc = "CONF0_SYNC (rw) register accessor: Configuration register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`conf0_sync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf0_sync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf0_sync`] module"]
242pub type CONF0_SYNC = crate::Reg<conf0_sync::CONF0_SYNC_SPEC>;
243#[doc = "Configuration register 0"]
244pub mod conf0_sync;
245#[doc = "CONF1 (rw) register accessor: Configuration register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`conf1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf1`] module"]
246pub type CONF1 = crate::Reg<conf1::CONF1_SPEC>;
247#[doc = "Configuration register 1"]
248pub mod conf1;
249#[doc = "HWFC_CONF_SYNC (rw) register accessor: Hardware flow-control configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`hwfc_conf_sync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwfc_conf_sync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwfc_conf_sync`] module"]
250pub type HWFC_CONF_SYNC = crate::Reg<hwfc_conf_sync::HWFC_CONF_SYNC_SPEC>;
251#[doc = "Hardware flow-control configuration"]
252pub mod hwfc_conf_sync;
253#[doc = "SLEEP_CONF0 (rw) register accessor: UART sleep configure register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sleep_conf0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sleep_conf0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sleep_conf0`] module"]
254pub type SLEEP_CONF0 = crate::Reg<sleep_conf0::SLEEP_CONF0_SPEC>;
255#[doc = "UART sleep configure register 0"]
256pub mod sleep_conf0;
257#[doc = "SLEEP_CONF1 (rw) register accessor: UART sleep configure register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sleep_conf1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sleep_conf1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sleep_conf1`] module"]
258pub type SLEEP_CONF1 = crate::Reg<sleep_conf1::SLEEP_CONF1_SPEC>;
259#[doc = "UART sleep configure register 1"]
260pub mod sleep_conf1;
261#[doc = "SLEEP_CONF2 (rw) register accessor: UART sleep configure register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sleep_conf2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sleep_conf2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sleep_conf2`] module"]
262pub type SLEEP_CONF2 = crate::Reg<sleep_conf2::SLEEP_CONF2_SPEC>;
263#[doc = "UART sleep configure register 2"]
264pub mod sleep_conf2;
265#[doc = "SWFC_CONF0_SYNC (rw) register accessor: Software flow-control character configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`swfc_conf0_sync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swfc_conf0_sync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swfc_conf0_sync`] module"]
266pub type SWFC_CONF0_SYNC = crate::Reg<swfc_conf0_sync::SWFC_CONF0_SYNC_SPEC>;
267#[doc = "Software flow-control character configuration"]
268pub mod swfc_conf0_sync;
269#[doc = "SWFC_CONF1 (rw) register accessor: Software flow-control character configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`swfc_conf1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swfc_conf1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swfc_conf1`] module"]
270pub type SWFC_CONF1 = crate::Reg<swfc_conf1::SWFC_CONF1_SPEC>;
271#[doc = "Software flow-control character configuration"]
272pub mod swfc_conf1;
273#[doc = "TXBRK_CONF_SYNC (rw) register accessor: Tx Break character configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`txbrk_conf_sync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbrk_conf_sync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbrk_conf_sync`] module"]
274pub type TXBRK_CONF_SYNC = crate::Reg<txbrk_conf_sync::TXBRK_CONF_SYNC_SPEC>;
275#[doc = "Tx Break character configuration"]
276pub mod txbrk_conf_sync;
277#[doc = "IDLE_CONF_SYNC (rw) register accessor: Frame-end idle configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`idle_conf_sync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`idle_conf_sync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idle_conf_sync`] module"]
278pub type IDLE_CONF_SYNC = crate::Reg<idle_conf_sync::IDLE_CONF_SYNC_SPEC>;
279#[doc = "Frame-end idle configuration"]
280pub mod idle_conf_sync;
281#[doc = "RS485_CONF_SYNC (rw) register accessor: RS485 mode configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rs485_conf_sync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rs485_conf_sync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rs485_conf_sync`] module"]
282pub type RS485_CONF_SYNC = crate::Reg<rs485_conf_sync::RS485_CONF_SYNC_SPEC>;
283#[doc = "RS485 mode configuration"]
284pub mod rs485_conf_sync;
285#[doc = "AT_CMD_PRECNT_SYNC (rw) register accessor: Pre-sequence timing configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`at_cmd_precnt_sync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`at_cmd_precnt_sync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@at_cmd_precnt_sync`] module"]
286pub type AT_CMD_PRECNT_SYNC = crate::Reg<at_cmd_precnt_sync::AT_CMD_PRECNT_SYNC_SPEC>;
287#[doc = "Pre-sequence timing configuration"]
288pub mod at_cmd_precnt_sync;
289#[doc = "AT_CMD_POSTCNT_SYNC (rw) register accessor: Post-sequence timing configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`at_cmd_postcnt_sync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`at_cmd_postcnt_sync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@at_cmd_postcnt_sync`] module"]
290pub type AT_CMD_POSTCNT_SYNC = crate::Reg<at_cmd_postcnt_sync::AT_CMD_POSTCNT_SYNC_SPEC>;
291#[doc = "Post-sequence timing configuration"]
292pub mod at_cmd_postcnt_sync;
293#[doc = "AT_CMD_GAPTOUT_SYNC (rw) register accessor: Timeout configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`at_cmd_gaptout_sync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`at_cmd_gaptout_sync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@at_cmd_gaptout_sync`] module"]
294pub type AT_CMD_GAPTOUT_SYNC = crate::Reg<at_cmd_gaptout_sync::AT_CMD_GAPTOUT_SYNC_SPEC>;
295#[doc = "Timeout configuration"]
296pub mod at_cmd_gaptout_sync;
297#[doc = "AT_CMD_CHAR_SYNC (rw) register accessor: AT escape sequence detection configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`at_cmd_char_sync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`at_cmd_char_sync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@at_cmd_char_sync`] module"]
298pub type AT_CMD_CHAR_SYNC = crate::Reg<at_cmd_char_sync::AT_CMD_CHAR_SYNC_SPEC>;
299#[doc = "AT escape sequence detection configuration"]
300pub mod at_cmd_char_sync;
301#[doc = "MEM_CONF (rw) register accessor: UART memory power configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`mem_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mem_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_conf`] module"]
302pub type MEM_CONF = crate::Reg<mem_conf::MEM_CONF_SPEC>;
303#[doc = "UART memory power configuration"]
304pub mod mem_conf;
305#[doc = "TOUT_CONF_SYNC (rw) register accessor: UART threshold and allocation configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`tout_conf_sync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tout_conf_sync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tout_conf_sync`] module"]
306pub type TOUT_CONF_SYNC = crate::Reg<tout_conf_sync::TOUT_CONF_SYNC_SPEC>;
307#[doc = "UART threshold and allocation configuration"]
308pub mod tout_conf_sync;
309#[doc = "MEM_TX_STATUS (r) register accessor: Tx-SRAM write and read offset address.\n\nYou can [`read`](crate::Reg::read) this register and get [`mem_tx_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_tx_status`] module"]
310pub type MEM_TX_STATUS = crate::Reg<mem_tx_status::MEM_TX_STATUS_SPEC>;
311#[doc = "Tx-SRAM write and read offset address."]
312pub mod mem_tx_status;
313#[doc = "MEM_RX_STATUS (r) register accessor: Rx-SRAM write and read offset address.\n\nYou can [`read`](crate::Reg::read) this register and get [`mem_rx_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_rx_status`] module"]
314pub type MEM_RX_STATUS = crate::Reg<mem_rx_status::MEM_RX_STATUS_SPEC>;
315#[doc = "Rx-SRAM write and read offset address."]
316pub mod mem_rx_status;
317#[doc = "FSM_STATUS (r) register accessor: UART transmit and receive status.\n\nYou can [`read`](crate::Reg::read) this register and get [`fsm_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsm_status`] module"]
318pub type FSM_STATUS = crate::Reg<fsm_status::FSM_STATUS_SPEC>;
319#[doc = "UART transmit and receive status."]
320pub mod fsm_status;
321#[doc = "CLK_CONF (rw) register accessor: UART core clock configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_conf`] module"]
322pub type CLK_CONF = crate::Reg<clk_conf::CLK_CONF_SPEC>;
323#[doc = "UART core clock configuration"]
324pub mod clk_conf;
325#[doc = "DATE (rw) register accessor: UART Version register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"]
326pub type DATE = crate::Reg<date::DATE_SPEC>;
327#[doc = "UART Version register"]
328pub mod date;
329#[doc = "AFIFO_STATUS (r) register accessor: UART AFIFO Status\n\nYou can [`read`](crate::Reg::read) this register and get [`afifo_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@afifo_status`] module"]
330pub type AFIFO_STATUS = crate::Reg<afifo_status::AFIFO_STATUS_SPEC>;
331#[doc = "UART AFIFO Status"]
332pub mod afifo_status;
333#[doc = "REG_UPDATE (rw) register accessor: UART Registers Configuration Update register\n\nYou can [`read`](crate::Reg::read) this register and get [`reg_update::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg_update::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_update`] module"]
334pub type REG_UPDATE = crate::Reg<reg_update::REG_UPDATE_SPEC>;
335#[doc = "UART Registers Configuration Update register"]
336pub mod reg_update;
337#[doc = "ID (rw) register accessor: UART ID register\n\nYou can [`read`](crate::Reg::read) this register and get [`id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id`] module"]
338pub type ID = crate::Reg<id::ID_SPEC>;
339#[doc = "UART ID register"]
340pub mod id;