Struct esp32c6_lp::lp_uart::clkdiv_sync::CLKDIV_SYNC_SPEC

pub struct CLKDIV_SYNC_SPEC;

Clock divider configuration

You can read this register and get clkdiv_sync::R. You can reset, write, write_with_zero this register using clkdiv_sync::W. You can also modify this register. See API.

Trait Implementations

impl RegisterSpec for CLKDIV_SYNC_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for CLKDIV_SYNC_SPEC

reset() method sets CLKDIV_SYNC to value 0x02b6

const RESET_VALUE: u32 = 694u32

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for CLKDIV_SYNC_SPEC

write(|w| ..) method takes clkdiv_sync::W writer structure

type Safety = Unsafe

Is it safe to write any bits to register

const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1

impl Readable for CLKDIV_SYNC_SPEC

read() method returns clkdiv_sync::R reader structure