Type Alias esp32c3::uart0::clk_conf::W

pub type W = W<CLK_CONF_SPEC>;

Register CLK_CONF writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn sclk_div_b(&mut self) -> SCLK_DIV_B_W<'_, CLK_CONF_SPEC>

Bits 0:5 - The denominator of the frequency divider factor.

pub fn sclk_div_a(&mut self) -> SCLK_DIV_A_W<'_, CLK_CONF_SPEC>

Bits 6:11 - The numerator of the frequency divider factor.

pub fn sclk_div_num(&mut self) -> SCLK_DIV_NUM_W<'_, CLK_CONF_SPEC>

Bits 12:19 - The integral part of the frequency divider factor.

pub fn sclk_sel(&mut self) -> SCLK_SEL_W<'_, CLK_CONF_SPEC>

Bits 20:21 - UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.

pub fn sclk_en(&mut self) -> SCLK_EN_W<'_, CLK_CONF_SPEC>

Bit 22 - Set this bit to enable UART Tx/Rx clock.

pub fn rst_core(&mut self) -> RST_CORE_W<'_, CLK_CONF_SPEC>

Bit 23 - Write 1 then write 0 to this bit, reset UART Tx/Rx.

pub fn tx_sclk_en(&mut self) -> TX_SCLK_EN_W<'_, CLK_CONF_SPEC>

Bit 24 - Set this bit to enable UART Tx clock.

pub fn rx_sclk_en(&mut self) -> RX_SCLK_EN_W<'_, CLK_CONF_SPEC>

Bit 25 - Set this bit to enable UART Rx clock.

pub fn tx_rst_core(&mut self) -> TX_RST_CORE_W<'_, CLK_CONF_SPEC>

Bit 26 - Write 1 then write 0 to this bit, reset UART Tx.

pub fn rx_rst_core(&mut self) -> RX_RST_CORE_W<'_, CLK_CONF_SPEC>

Bit 27 - Write 1 then write 0 to this bit, reset UART Rx.