Expand description
UART core clock configuration
Structs§
- UART core clock configuration
Type Aliases§
- Register
CLK_CONF
reader - Field
RST_CORE
reader - Write 1 then write 0 to this bit, reset UART Tx/Rx. - Field
RST_CORE
writer - Write 1 then write 0 to this bit, reset UART Tx/Rx. - Field
RX_RST_CORE
reader - Write 1 then write 0 to this bit, reset UART Rx. - Field
RX_RST_CORE
writer - Write 1 then write 0 to this bit, reset UART Rx. - Field
RX_SCLK_EN
reader - Set this bit to enable UART Rx clock. - Field
RX_SCLK_EN
writer - Set this bit to enable UART Rx clock. - Field
SCLK_DIV_A
reader - The numerator of the frequency divider factor. - Field
SCLK_DIV_A
writer - The numerator of the frequency divider factor. - Field
SCLK_DIV_B
reader - The denominator of the frequency divider factor. - Field
SCLK_DIV_B
writer - The denominator of the frequency divider factor. - Field
SCLK_DIV_NUM
reader - The integral part of the frequency divider factor. - Field
SCLK_DIV_NUM
writer - The integral part of the frequency divider factor. - Field
SCLK_EN
reader - Set this bit to enable UART Tx/Rx clock. - Field
SCLK_EN
writer - Set this bit to enable UART Tx/Rx clock. - Field
SCLK_SEL
reader - UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL. - Field
SCLK_SEL
writer - UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL. - Field
TX_RST_CORE
reader - Write 1 then write 0 to this bit, reset UART Tx. - Field
TX_RST_CORE
writer - Write 1 then write 0 to this bit, reset UART Tx. - Field
TX_SCLK_EN
reader - Set this bit to enable UART Tx clock. - Field
TX_SCLK_EN
writer - Set this bit to enable UART Tx clock. - Register
CLK_CONF
writer