Type Alias esp32c3::sensitive::core_x_iram0_dram0_dma_split_line_constrain_5::W

pub type W = W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_SPEC>;

Register CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5 writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn core_x_dram0_dma_sram_line_1_category_0( &mut self ) -> CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_W<'_, CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_SPEC>

Bits 0:1 - core_x_dram0_dma_sram_line_1_category_0

pub fn core_x_dram0_dma_sram_line_1_category_1( &mut self ) -> CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_W<'_, CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_SPEC>

Bits 2:3 - core_x_dram0_dma_sram_line_1_category_1

pub fn core_x_dram0_dma_sram_line_1_category_2( &mut self ) -> CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_W<'_, CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_SPEC>

Bits 4:5 - core_x_dram0_dma_sram_line_1_category_2

pub fn core_x_dram0_dma_sram_line_1_splitaddr( &mut self ) -> CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_W<'_, CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_SPEC>

Bits 14:21 - core_x_dram0_dma_sram_line_1_splitaddr