Type Alias esp32c3::sensitive::core_x_iram0_dram0_dma_split_line_constrain_4::W
source · pub type W = W<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_SPEC>;
Expand description
Register CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4
writer
Aliased Type§
struct W { /* private fields */ }
Implementations§
source§impl W
impl W
sourcepub fn core_x_dram0_dma_sram_line_0_category_0(
&mut self
) -> CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_W<'_, CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_SPEC>
pub fn core_x_dram0_dma_sram_line_0_category_0( &mut self ) -> CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_W<'_, CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_SPEC>
Bits 0:1 - core_x_dram0_dma_sram_line_0_category_0
sourcepub fn core_x_dram0_dma_sram_line_0_category_1(
&mut self
) -> CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_W<'_, CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_SPEC>
pub fn core_x_dram0_dma_sram_line_0_category_1( &mut self ) -> CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_W<'_, CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_SPEC>
Bits 2:3 - core_x_dram0_dma_sram_line_0_category_1
sourcepub fn core_x_dram0_dma_sram_line_0_category_2(
&mut self
) -> CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_W<'_, CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_SPEC>
pub fn core_x_dram0_dma_sram_line_0_category_2( &mut self ) -> CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_W<'_, CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_SPEC>
Bits 4:5 - core_x_dram0_dma_sram_line_0_category_2
sourcepub fn core_x_dram0_dma_sram_line_0_splitaddr(
&mut self
) -> CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_W<'_, CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_SPEC>
pub fn core_x_dram0_dma_sram_line_0_splitaddr( &mut self ) -> CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_W<'_, CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_SPEC>
Bits 14:21 - core_x_dram0_dma_sram_line_0_splitaddr