Type Alias esp32c3::i2s0::tx_clkm_conf::W

pub type W = W<TX_CLKM_CONF_SPEC>;

Register TX_CLKM_CONF writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn tx_clkm_div_num(&mut self) -> TX_CLKM_DIV_NUM_W<'_, TX_CLKM_CONF_SPEC>

Bits 0:7 - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div.

pub fn tx_clk_active(&mut self) -> TX_CLK_ACTIVE_W<'_, TX_CLKM_CONF_SPEC>

Bit 26 - I2S Tx module clock enable signal.

pub fn tx_clk_sel(&mut self) -> TX_CLK_SEL_W<'_, TX_CLKM_CONF_SPEC>

Bits 27:28 - Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.

pub fn clk_en(&mut self) -> CLK_EN_W<'_, TX_CLKM_CONF_SPEC>

Bit 29 - Set this bit to enable clk gate