Module esp32c3::i2s0::tx_clkm_conf

I2S TX clock configure register

Structs

• TX_CLKM_CONF_SPEC
  I2S TX clock configure register

Type Aliases

• CLK_EN_R
  Field CLK_EN reader - Set this bit to enable clk gate
• CLK_EN_W
  Field CLK_EN writer - Set this bit to enable clk gate
• R
  Register TX_CLKM_CONF reader
• TX_CLKM_DIV_NUM_R
  Field TX_CLKM_DIV_NUM reader - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div.
• TX_CLKM_DIV_NUM_W
  Field TX_CLKM_DIV_NUM writer - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div.
• TX_CLK_ACTIVE_R
  Field TX_CLK_ACTIVE reader - I2S Tx module clock enable signal.
• TX_CLK_ACTIVE_W
  Field TX_CLK_ACTIVE writer - I2S Tx module clock enable signal.
• TX_CLK_SEL_R
  Field TX_CLK_SEL reader - Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
• TX_CLK_SEL_W
  Field TX_CLK_SEL writer - Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
• W
  Register TX_CLKM_CONF writer