Type Alias esp32c3::i2s0::rx_conf::W

pub type W = W<RX_CONF_SPEC>;

Register RX_CONF writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn rx_reset(&mut self) -> RX_RESET_W<'_, RX_CONF_SPEC>

Bit 0 - Set this bit to reset receiver

pub fn rx_fifo_reset(&mut self) -> RX_FIFO_RESET_W<'_, RX_CONF_SPEC>

Bit 1 - Set this bit to reset Rx AFIFO

pub fn rx_start(&mut self) -> RX_START_W<'_, RX_CONF_SPEC>

Bit 2 - Set this bit to start receiving data

pub fn rx_slave_mod(&mut self) -> RX_SLAVE_MOD_W<'_, RX_CONF_SPEC>

Bit 3 - Set this bit to enable slave receiver mode

pub fn rx_mono(&mut self) -> RX_MONO_W<'_, RX_CONF_SPEC>

Bit 5 - Set this bit to enable receiver in mono mode

pub fn rx_big_endian(&mut self) -> RX_BIG_ENDIAN_W<'_, RX_CONF_SPEC>

Bit 7 - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.

pub fn rx_update(&mut self) -> RX_UPDATE_W<'_, RX_CONF_SPEC>

Bit 8 - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.

pub fn rx_mono_fst_vld(&mut self) -> RX_MONO_FST_VLD_W<'_, RX_CONF_SPEC>

Bit 9 - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode.

pub fn rx_pcm_conf(&mut self) -> RX_PCM_CONF_W<'_, RX_CONF_SPEC>

Bits 10:11 - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &

pub fn rx_pcm_bypass(&mut self) -> RX_PCM_BYPASS_W<'_, RX_CONF_SPEC>

Bit 12 - Set this bit to bypass Compress/Decompress module for received data.

pub fn rx_stop_mode(&mut self) -> RX_STOP_MODE_W<'_, RX_CONF_SPEC>

Bits 13:14 - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.

pub fn rx_left_align(&mut self) -> RX_LEFT_ALIGN_W<'_, RX_CONF_SPEC>

Bit 15 - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode.

pub fn rx_24_fill_en(&mut self) -> RX_24_FILL_EN_W<'_, RX_CONF_SPEC>

Bit 16 - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.

pub fn rx_ws_idle_pol(&mut self) -> RX_WS_IDLE_POL_W<'_, RX_CONF_SPEC>

Bit 17 - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel.

pub fn rx_bit_order(&mut self) -> RX_BIT_ORDER_W<'_, RX_CONF_SPEC>

Bit 18 - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.

pub fn rx_tdm_en(&mut self) -> RX_TDM_EN_W<'_, RX_CONF_SPEC>

Bit 19 - 1: Enable I2S TDM Rx mode . 0: Disable.

pub fn rx_pdm_en(&mut self) -> RX_PDM_EN_W<'_, RX_CONF_SPEC>

Bit 20 - 1: Enable I2S PDM Rx mode . 0: Disable.