Module esp32c3::i2s0::rx_conf

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I2S RX configure register

Structs§

Type Aliases§

  • R
    Register RX_CONF reader
  • RX_24_FILL_EN_R
    Field RX_24_FILL_EN reader - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
  • RX_24_FILL_EN_W
    Field RX_24_FILL_EN writer - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
  • RX_BIG_ENDIAN_R
    Field RX_BIG_ENDIAN reader - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
  • RX_BIG_ENDIAN_W
    Field RX_BIG_ENDIAN writer - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
  • RX_BIT_ORDER_R
    Field RX_BIT_ORDER reader - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.
  • RX_BIT_ORDER_W
    Field RX_BIT_ORDER writer - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.
  • RX_FIFO_RESET_W
    Field RX_FIFO_RESET writer - Set this bit to reset Rx AFIFO
  • RX_LEFT_ALIGN_R
    Field RX_LEFT_ALIGN reader - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
  • RX_LEFT_ALIGN_W
    Field RX_LEFT_ALIGN writer - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
  • RX_MONO_FST_VLD_R
    Field RX_MONO_FST_VLD reader - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode.
  • RX_MONO_FST_VLD_W
    Field RX_MONO_FST_VLD writer - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode.
  • RX_MONO_R
    Field RX_MONO reader - Set this bit to enable receiver in mono mode
  • RX_MONO_W
    Field RX_MONO writer - Set this bit to enable receiver in mono mode
  • RX_PCM_BYPASS_R
    Field RX_PCM_BYPASS reader - Set this bit to bypass Compress/Decompress module for received data.
  • RX_PCM_BYPASS_W
    Field RX_PCM_BYPASS writer - Set this bit to bypass Compress/Decompress module for received data.
  • RX_PCM_CONF_R
    Field RX_PCM_CONF reader - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
  • RX_PCM_CONF_W
    Field RX_PCM_CONF writer - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
  • RX_PDM_EN_R
    Field RX_PDM_EN reader - 1: Enable I2S PDM Rx mode . 0: Disable.
  • RX_PDM_EN_W
    Field RX_PDM_EN writer - 1: Enable I2S PDM Rx mode . 0: Disable.
  • RX_RESET_W
    Field RX_RESET writer - Set this bit to reset receiver
  • RX_SLAVE_MOD_R
    Field RX_SLAVE_MOD reader - Set this bit to enable slave receiver mode
  • RX_SLAVE_MOD_W
    Field RX_SLAVE_MOD writer - Set this bit to enable slave receiver mode
  • RX_START_R
    Field RX_START reader - Set this bit to start receiving data
  • RX_START_W
    Field RX_START writer - Set this bit to start receiving data
  • RX_STOP_MODE_R
    Field RX_STOP_MODE reader - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
  • RX_STOP_MODE_W
    Field RX_STOP_MODE writer - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
  • RX_TDM_EN_R
    Field RX_TDM_EN reader - 1: Enable I2S TDM Rx mode . 0: Disable.
  • RX_TDM_EN_W
    Field RX_TDM_EN writer - 1: Enable I2S TDM Rx mode . 0: Disable.
  • RX_UPDATE_R
    Field RX_UPDATE reader - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.
  • RX_UPDATE_W
    Field RX_UPDATE writer - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.
  • RX_WS_IDLE_POL_R
    Field RX_WS_IDLE_POL reader - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
  • RX_WS_IDLE_POL_W
    Field RX_WS_IDLE_POL writer - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
  • W
    Register RX_CONF writer