Module esp32c3::spi2::user1

SPI USER control register 1

Structs

• USER1_SPEC
  SPI USER control register 1

Type Aliases

• CS_HOLD_TIME_R
  Field CS_HOLD_TIME reader - delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.
• CS_HOLD_TIME_W
  Field CS_HOLD_TIME writer - delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.
• CS_SETUP_TIME_R
  Field CS_SETUP_TIME reader - (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.
• CS_SETUP_TIME_W
  Field CS_SETUP_TIME writer - (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.
• MST_WFULL_ERR_END_EN_R
  Field MST_WFULL_ERR_END_EN reader - 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.
• MST_WFULL_ERR_END_EN_W
  Field MST_WFULL_ERR_END_EN writer - 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.
• R
  Register USER1 reader
• USR_ADDR_BITLEN_R
  Field USR_ADDR_BITLEN reader - The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.
• USR_ADDR_BITLEN_W
  Field USR_ADDR_BITLEN writer - The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.
• USR_DUMMY_CYCLELEN_R
  Field USR_DUMMY_CYCLELEN reader - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.
• USR_DUMMY_CYCLELEN_W
  Field USR_DUMMY_CYCLELEN writer - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.
• W
  Register USER1 writer