Type Alias esp32c3::spi2::clk_gate::R

pub type R = R<CLK_GATE_SPEC>;

Register CLK_GATE reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn clk_en(&self) -> CLK_EN_R

Bit 0 - Set this bit to enable clk gate

pub fn mst_clk_active(&self) -> MST_CLK_ACTIVE_R

Bit 1 - Set this bit to power on the SPI module clock.

pub fn mst_clk_sel(&self) -> MST_CLK_SEL_R

Bit 2 - This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.