Struct esp32c3::extmem::cache_sync_int_ctrl::W

pub struct W(_);

Register CACHE_SYNC_INT_CTRL writer

Implementations

impl W

pub fn icache_sync_int_ena(&mut self) -> ICACHE_SYNC_INT_ENA_W<'_, 1>

Bit 1 - The bit is used to enable the interrupt by icache sync done.

pub fn icache_sync_int_clr(&mut self) -> ICACHE_SYNC_INT_CLR_W<'_, 2>

Bit 2 - The bit is used to clear the interrupt by icache sync done.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<CACHE_SYNC_INT_CTRL_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CACHE_SYNC_INT_CTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<CACHE_SYNC_INT_CTRL_SPEC>> for W

fn from(writer: W<CACHE_SYNC_INT_CTRL_SPEC>) -> Self

Converts to this type from the input type.