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#[doc = "Register `DBUS_ACS_FLASH_MISS_CNT` reader"]
pub struct R(crate::R<DBUS_ACS_FLASH_MISS_CNT_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<DBUS_ACS_FLASH_MISS_CNT_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl From<crate::R<DBUS_ACS_FLASH_MISS_CNT_SPEC>> for R {
    #[inline(always)]
    fn from(reader: crate::R<DBUS_ACS_FLASH_MISS_CNT_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Field `DBUS_ACS_FLASH_MISS_CNT` reader - The bits are used to count the number of the cache miss caused by dbus access flash."]
pub struct DBUS_ACS_FLASH_MISS_CNT_R(crate::FieldReader<u32, u32>);
impl DBUS_ACS_FLASH_MISS_CNT_R {
    #[inline(always)]
    pub(crate) fn new(bits: u32) -> Self {
        DBUS_ACS_FLASH_MISS_CNT_R(crate::FieldReader::new(bits))
    }
}
impl core::ops::Deref for DBUS_ACS_FLASH_MISS_CNT_R {
    type Target = crate::FieldReader<u32, u32>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl R {
    #[doc = "Bits 0:31 - The bits are used to count the number of the cache miss caused by dbus access flash."]
    #[inline(always)]
    pub fn dbus_acs_flash_miss_cnt(&self) -> DBUS_ACS_FLASH_MISS_CNT_R {
        DBUS_ACS_FLASH_MISS_CNT_R::new(self.bits)
    }
}
#[doc = "This description will be updated in the near future.\n\nThis register you can [`read`]
(crate::generic::Reg::read). See [API]
(https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbus_acs_flash_miss_cnt]
(index.html) module"]
pub struct DBUS_ACS_FLASH_MISS_CNT_SPEC;
impl crate::RegisterSpec for DBUS_ACS_FLASH_MISS_CNT_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [dbus_acs_flash_miss_cnt::R]
(R) reader structure"]
impl crate::Readable for DBUS_ACS_FLASH_MISS_CNT_SPEC {
    type Reader = R;
}
#[doc = "`reset()` method sets DBUS_ACS_FLASH_MISS_CNT to value 0"]
impl crate::Resettable for DBUS_ACS_FLASH_MISS_CNT_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}