1#[doc = "Register `INT_ENA` reader"]
2pub type R = crate::R<INT_ENA_SPEC>;
3#[doc = "Register `INT_ENA` writer"]
4pub type W = crate::W<INT_ENA_SPEC>;
5#[doc = "Field `RXFIFO_WM` reader - reg_rxfifo_wm_int_ena"]
6pub type RXFIFO_WM_R = crate::BitReader;
7#[doc = "Field `RXFIFO_WM` writer - reg_rxfifo_wm_int_ena"]
8pub type RXFIFO_WM_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TXFIFO_WM` reader - reg_txfifo_wm_int_ena"]
10pub type TXFIFO_WM_R = crate::BitReader;
11#[doc = "Field `TXFIFO_WM` writer - reg_txfifo_wm_int_ena"]
12pub type TXFIFO_WM_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RXFIFO_OVF` reader - reg_rxfifo_ovf_int_ena"]
14pub type RXFIFO_OVF_R = crate::BitReader;
15#[doc = "Field `RXFIFO_OVF` writer - reg_rxfifo_ovf_int_ena"]
16pub type RXFIFO_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `END_DETECT` reader - reg_end_detect_int_ena"]
18pub type END_DETECT_R = crate::BitReader;
19#[doc = "Field `END_DETECT` writer - reg_end_detect_int_ena"]
20pub type END_DETECT_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `BYTE_TRANS_DONE` reader - reg_byte_trans_done_int_ena"]
22pub type BYTE_TRANS_DONE_R = crate::BitReader;
23#[doc = "Field `BYTE_TRANS_DONE` writer - reg_byte_trans_done_int_ena"]
24pub type BYTE_TRANS_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `ARBITRATION_LOST` reader - reg_arbitration_lost_int_ena"]
26pub type ARBITRATION_LOST_R = crate::BitReader;
27#[doc = "Field `ARBITRATION_LOST` writer - reg_arbitration_lost_int_ena"]
28pub type ARBITRATION_LOST_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `MST_TXFIFO_UDF` reader - reg_mst_txfifo_udf_int_ena"]
30pub type MST_TXFIFO_UDF_R = crate::BitReader;
31#[doc = "Field `MST_TXFIFO_UDF` writer - reg_mst_txfifo_udf_int_ena"]
32pub type MST_TXFIFO_UDF_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `TRANS_COMPLETE` reader - reg_trans_complete_int_ena"]
34pub type TRANS_COMPLETE_R = crate::BitReader;
35#[doc = "Field `TRANS_COMPLETE` writer - reg_trans_complete_int_ena"]
36pub type TRANS_COMPLETE_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `TIME_OUT` reader - reg_time_out_int_ena"]
38pub type TIME_OUT_R = crate::BitReader;
39#[doc = "Field `TIME_OUT` writer - reg_time_out_int_ena"]
40pub type TIME_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `TRANS_START` reader - reg_trans_start_int_ena"]
42pub type TRANS_START_R = crate::BitReader;
43#[doc = "Field `TRANS_START` writer - reg_trans_start_int_ena"]
44pub type TRANS_START_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `NACK` reader - reg_nack_int_ena"]
46pub type NACK_R = crate::BitReader;
47#[doc = "Field `NACK` writer - reg_nack_int_ena"]
48pub type NACK_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `TXFIFO_OVF` reader - reg_txfifo_ovf_int_ena"]
50pub type TXFIFO_OVF_R = crate::BitReader;
51#[doc = "Field `TXFIFO_OVF` writer - reg_txfifo_ovf_int_ena"]
52pub type TXFIFO_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `RXFIFO_UDF` reader - reg_rxfifo_udf_int_ena"]
54pub type RXFIFO_UDF_R = crate::BitReader;
55#[doc = "Field `RXFIFO_UDF` writer - reg_rxfifo_udf_int_ena"]
56pub type RXFIFO_UDF_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `SCL_ST_TO` reader - reg_scl_st_to_int_ena"]
58pub type SCL_ST_TO_R = crate::BitReader;
59#[doc = "Field `SCL_ST_TO` writer - reg_scl_st_to_int_ena"]
60pub type SCL_ST_TO_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `SCL_MAIN_ST_TO` reader - reg_scl_main_st_to_int_ena"]
62pub type SCL_MAIN_ST_TO_R = crate::BitReader;
63#[doc = "Field `SCL_MAIN_ST_TO` writer - reg_scl_main_st_to_int_ena"]
64pub type SCL_MAIN_ST_TO_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `DET_START` reader - reg_det_start_int_ena"]
66pub type DET_START_R = crate::BitReader;
67#[doc = "Field `DET_START` writer - reg_det_start_int_ena"]
68pub type DET_START_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `SLAVE_STRETCH` reader - reg_slave_stretch_int_ena"]
70pub type SLAVE_STRETCH_R = crate::BitReader;
71#[doc = "Field `SLAVE_STRETCH` writer - reg_slave_stretch_int_ena"]
72pub type SLAVE_STRETCH_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `GENERAL_CALL` reader - reg_general_call_int_ena"]
74pub type GENERAL_CALL_R = crate::BitReader;
75#[doc = "Field `GENERAL_CALL` writer - reg_general_call_int_ena"]
76pub type GENERAL_CALL_W<'a, REG> = crate::BitWriter<'a, REG>;
77impl R {
78 #[doc = "Bit 0 - reg_rxfifo_wm_int_ena"]
79 #[inline(always)]
80 pub fn rxfifo_wm(&self) -> RXFIFO_WM_R {
81 RXFIFO_WM_R::new((self.bits & 1) != 0)
82 }
83 #[doc = "Bit 1 - reg_txfifo_wm_int_ena"]
84 #[inline(always)]
85 pub fn txfifo_wm(&self) -> TXFIFO_WM_R {
86 TXFIFO_WM_R::new(((self.bits >> 1) & 1) != 0)
87 }
88 #[doc = "Bit 2 - reg_rxfifo_ovf_int_ena"]
89 #[inline(always)]
90 pub fn rxfifo_ovf(&self) -> RXFIFO_OVF_R {
91 RXFIFO_OVF_R::new(((self.bits >> 2) & 1) != 0)
92 }
93 #[doc = "Bit 3 - reg_end_detect_int_ena"]
94 #[inline(always)]
95 pub fn end_detect(&self) -> END_DETECT_R {
96 END_DETECT_R::new(((self.bits >> 3) & 1) != 0)
97 }
98 #[doc = "Bit 4 - reg_byte_trans_done_int_ena"]
99 #[inline(always)]
100 pub fn byte_trans_done(&self) -> BYTE_TRANS_DONE_R {
101 BYTE_TRANS_DONE_R::new(((self.bits >> 4) & 1) != 0)
102 }
103 #[doc = "Bit 5 - reg_arbitration_lost_int_ena"]
104 #[inline(always)]
105 pub fn arbitration_lost(&self) -> ARBITRATION_LOST_R {
106 ARBITRATION_LOST_R::new(((self.bits >> 5) & 1) != 0)
107 }
108 #[doc = "Bit 6 - reg_mst_txfifo_udf_int_ena"]
109 #[inline(always)]
110 pub fn mst_txfifo_udf(&self) -> MST_TXFIFO_UDF_R {
111 MST_TXFIFO_UDF_R::new(((self.bits >> 6) & 1) != 0)
112 }
113 #[doc = "Bit 7 - reg_trans_complete_int_ena"]
114 #[inline(always)]
115 pub fn trans_complete(&self) -> TRANS_COMPLETE_R {
116 TRANS_COMPLETE_R::new(((self.bits >> 7) & 1) != 0)
117 }
118 #[doc = "Bit 8 - reg_time_out_int_ena"]
119 #[inline(always)]
120 pub fn time_out(&self) -> TIME_OUT_R {
121 TIME_OUT_R::new(((self.bits >> 8) & 1) != 0)
122 }
123 #[doc = "Bit 9 - reg_trans_start_int_ena"]
124 #[inline(always)]
125 pub fn trans_start(&self) -> TRANS_START_R {
126 TRANS_START_R::new(((self.bits >> 9) & 1) != 0)
127 }
128 #[doc = "Bit 10 - reg_nack_int_ena"]
129 #[inline(always)]
130 pub fn nack(&self) -> NACK_R {
131 NACK_R::new(((self.bits >> 10) & 1) != 0)
132 }
133 #[doc = "Bit 11 - reg_txfifo_ovf_int_ena"]
134 #[inline(always)]
135 pub fn txfifo_ovf(&self) -> TXFIFO_OVF_R {
136 TXFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0)
137 }
138 #[doc = "Bit 12 - reg_rxfifo_udf_int_ena"]
139 #[inline(always)]
140 pub fn rxfifo_udf(&self) -> RXFIFO_UDF_R {
141 RXFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0)
142 }
143 #[doc = "Bit 13 - reg_scl_st_to_int_ena"]
144 #[inline(always)]
145 pub fn scl_st_to(&self) -> SCL_ST_TO_R {
146 SCL_ST_TO_R::new(((self.bits >> 13) & 1) != 0)
147 }
148 #[doc = "Bit 14 - reg_scl_main_st_to_int_ena"]
149 #[inline(always)]
150 pub fn scl_main_st_to(&self) -> SCL_MAIN_ST_TO_R {
151 SCL_MAIN_ST_TO_R::new(((self.bits >> 14) & 1) != 0)
152 }
153 #[doc = "Bit 15 - reg_det_start_int_ena"]
154 #[inline(always)]
155 pub fn det_start(&self) -> DET_START_R {
156 DET_START_R::new(((self.bits >> 15) & 1) != 0)
157 }
158 #[doc = "Bit 16 - reg_slave_stretch_int_ena"]
159 #[inline(always)]
160 pub fn slave_stretch(&self) -> SLAVE_STRETCH_R {
161 SLAVE_STRETCH_R::new(((self.bits >> 16) & 1) != 0)
162 }
163 #[doc = "Bit 17 - reg_general_call_int_ena"]
164 #[inline(always)]
165 pub fn general_call(&self) -> GENERAL_CALL_R {
166 GENERAL_CALL_R::new(((self.bits >> 17) & 1) != 0)
167 }
168}
169#[cfg(feature = "impl-register-debug")]
170impl core::fmt::Debug for R {
171 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
172 f.debug_struct("INT_ENA")
173 .field("rxfifo_wm", &self.rxfifo_wm())
174 .field("txfifo_wm", &self.txfifo_wm())
175 .field("rxfifo_ovf", &self.rxfifo_ovf())
176 .field("end_detect", &self.end_detect())
177 .field("byte_trans_done", &self.byte_trans_done())
178 .field("arbitration_lost", &self.arbitration_lost())
179 .field("mst_txfifo_udf", &self.mst_txfifo_udf())
180 .field("trans_complete", &self.trans_complete())
181 .field("time_out", &self.time_out())
182 .field("trans_start", &self.trans_start())
183 .field("nack", &self.nack())
184 .field("txfifo_ovf", &self.txfifo_ovf())
185 .field("rxfifo_udf", &self.rxfifo_udf())
186 .field("scl_st_to", &self.scl_st_to())
187 .field("scl_main_st_to", &self.scl_main_st_to())
188 .field("det_start", &self.det_start())
189 .field("slave_stretch", &self.slave_stretch())
190 .field("general_call", &self.general_call())
191 .finish()
192 }
193}
194impl W {
195 #[doc = "Bit 0 - reg_rxfifo_wm_int_ena"]
196 #[inline(always)]
197 pub fn rxfifo_wm(&mut self) -> RXFIFO_WM_W<INT_ENA_SPEC> {
198 RXFIFO_WM_W::new(self, 0)
199 }
200 #[doc = "Bit 1 - reg_txfifo_wm_int_ena"]
201 #[inline(always)]
202 pub fn txfifo_wm(&mut self) -> TXFIFO_WM_W<INT_ENA_SPEC> {
203 TXFIFO_WM_W::new(self, 1)
204 }
205 #[doc = "Bit 2 - reg_rxfifo_ovf_int_ena"]
206 #[inline(always)]
207 pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_ENA_SPEC> {
208 RXFIFO_OVF_W::new(self, 2)
209 }
210 #[doc = "Bit 3 - reg_end_detect_int_ena"]
211 #[inline(always)]
212 pub fn end_detect(&mut self) -> END_DETECT_W<INT_ENA_SPEC> {
213 END_DETECT_W::new(self, 3)
214 }
215 #[doc = "Bit 4 - reg_byte_trans_done_int_ena"]
216 #[inline(always)]
217 pub fn byte_trans_done(&mut self) -> BYTE_TRANS_DONE_W<INT_ENA_SPEC> {
218 BYTE_TRANS_DONE_W::new(self, 4)
219 }
220 #[doc = "Bit 5 - reg_arbitration_lost_int_ena"]
221 #[inline(always)]
222 pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_ENA_SPEC> {
223 ARBITRATION_LOST_W::new(self, 5)
224 }
225 #[doc = "Bit 6 - reg_mst_txfifo_udf_int_ena"]
226 #[inline(always)]
227 pub fn mst_txfifo_udf(&mut self) -> MST_TXFIFO_UDF_W<INT_ENA_SPEC> {
228 MST_TXFIFO_UDF_W::new(self, 6)
229 }
230 #[doc = "Bit 7 - reg_trans_complete_int_ena"]
231 #[inline(always)]
232 pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_ENA_SPEC> {
233 TRANS_COMPLETE_W::new(self, 7)
234 }
235 #[doc = "Bit 8 - reg_time_out_int_ena"]
236 #[inline(always)]
237 pub fn time_out(&mut self) -> TIME_OUT_W<INT_ENA_SPEC> {
238 TIME_OUT_W::new(self, 8)
239 }
240 #[doc = "Bit 9 - reg_trans_start_int_ena"]
241 #[inline(always)]
242 pub fn trans_start(&mut self) -> TRANS_START_W<INT_ENA_SPEC> {
243 TRANS_START_W::new(self, 9)
244 }
245 #[doc = "Bit 10 - reg_nack_int_ena"]
246 #[inline(always)]
247 pub fn nack(&mut self) -> NACK_W<INT_ENA_SPEC> {
248 NACK_W::new(self, 10)
249 }
250 #[doc = "Bit 11 - reg_txfifo_ovf_int_ena"]
251 #[inline(always)]
252 pub fn txfifo_ovf(&mut self) -> TXFIFO_OVF_W<INT_ENA_SPEC> {
253 TXFIFO_OVF_W::new(self, 11)
254 }
255 #[doc = "Bit 12 - reg_rxfifo_udf_int_ena"]
256 #[inline(always)]
257 pub fn rxfifo_udf(&mut self) -> RXFIFO_UDF_W<INT_ENA_SPEC> {
258 RXFIFO_UDF_W::new(self, 12)
259 }
260 #[doc = "Bit 13 - reg_scl_st_to_int_ena"]
261 #[inline(always)]
262 pub fn scl_st_to(&mut self) -> SCL_ST_TO_W<INT_ENA_SPEC> {
263 SCL_ST_TO_W::new(self, 13)
264 }
265 #[doc = "Bit 14 - reg_scl_main_st_to_int_ena"]
266 #[inline(always)]
267 pub fn scl_main_st_to(&mut self) -> SCL_MAIN_ST_TO_W<INT_ENA_SPEC> {
268 SCL_MAIN_ST_TO_W::new(self, 14)
269 }
270 #[doc = "Bit 15 - reg_det_start_int_ena"]
271 #[inline(always)]
272 pub fn det_start(&mut self) -> DET_START_W<INT_ENA_SPEC> {
273 DET_START_W::new(self, 15)
274 }
275 #[doc = "Bit 16 - reg_slave_stretch_int_ena"]
276 #[inline(always)]
277 pub fn slave_stretch(&mut self) -> SLAVE_STRETCH_W<INT_ENA_SPEC> {
278 SLAVE_STRETCH_W::new(self, 16)
279 }
280 #[doc = "Bit 17 - reg_general_call_int_ena"]
281 #[inline(always)]
282 pub fn general_call(&mut self) -> GENERAL_CALL_W<INT_ENA_SPEC> {
283 GENERAL_CALL_W::new(self, 17)
284 }
285}
286#[doc = "I2C_INT_ENA_REG\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
287pub struct INT_ENA_SPEC;
288impl crate::RegisterSpec for INT_ENA_SPEC {
289 type Ux = u32;
290}
291#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
292impl crate::Readable for INT_ENA_SPEC {}
293#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
294impl crate::Writable for INT_ENA_SPEC {
295 type Safety = crate::Unsafe;
296}
297#[doc = "`reset()` method sets INT_ENA to value 0"]
298impl crate::Resettable for INT_ENA_SPEC {}