1#[doc = "Register `CONF0` reader"]
2pub type R = crate::R<CONF0_SPEC>;
3#[doc = "Register `CONF0` writer"]
4pub type W = crate::W<CONF0_SPEC>;
5#[doc = "Field `TX_RST` reader - Write 1, then write 0 to this bit to reset decode state machine."]
6pub type TX_RST_R = crate::BitReader;
7#[doc = "Field `TX_RST` writer - Write 1, then write 0 to this bit to reset decode state machine."]
8pub type TX_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `RX_RST` reader - Write 1, then write 0 to this bit to reset encode state machine."]
10pub type RX_RST_R = crate::BitReader;
11#[doc = "Field `RX_RST` writer - Write 1, then write 0 to this bit to reset encode state machine."]
12pub type RX_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `UART0_CE` reader - Set this bit to link up HCI and UART0."]
14pub type UART0_CE_R = crate::BitReader;
15#[doc = "Field `UART0_CE` writer - Set this bit to link up HCI and UART0."]
16pub type UART0_CE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `UART1_CE` reader - Set this bit to link up HCI and UART1."]
18pub type UART1_CE_R = crate::BitReader;
19#[doc = "Field `UART1_CE` writer - Set this bit to link up HCI and UART1."]
20pub type UART1_CE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SEPER_EN` reader - Set this bit to separate the data frame using a special char."]
22pub type SEPER_EN_R = crate::BitReader;
23#[doc = "Field `SEPER_EN` writer - Set this bit to separate the data frame using a special char."]
24pub type SEPER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `HEAD_EN` reader - Set this bit to encode the data packet with a formatting header."]
26pub type HEAD_EN_R = crate::BitReader;
27#[doc = "Field `HEAD_EN` writer - Set this bit to encode the data packet with a formatting header."]
28pub type HEAD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `CRC_REC_EN` reader - Set this bit to enable UHCI to receive the 16 bit CRC."]
30pub type CRC_REC_EN_R = crate::BitReader;
31#[doc = "Field `CRC_REC_EN` writer - Set this bit to enable UHCI to receive the 16 bit CRC."]
32pub type CRC_REC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `UART_IDLE_EOF_EN` reader - If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state."]
34pub type UART_IDLE_EOF_EN_R = crate::BitReader;
35#[doc = "Field `UART_IDLE_EOF_EN` writer - If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state."]
36pub type UART_IDLE_EOF_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `LEN_EOF_EN` reader - If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received."]
38pub type LEN_EOF_EN_R = crate::BitReader;
39#[doc = "Field `LEN_EOF_EN` writer - If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received."]
40pub type LEN_EOF_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `ENCODE_CRC_EN` reader - Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload."]
42pub type ENCODE_CRC_EN_R = crate::BitReader;
43#[doc = "Field `ENCODE_CRC_EN` writer - Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload."]
44pub type ENCODE_CRC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `CLK_EN` reader - 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers."]
46pub type CLK_EN_R = crate::BitReader;
47#[doc = "Field `CLK_EN` writer - 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers."]
48pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `UART_RX_BRK_EOF_EN` reader - If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART."]
50pub type UART_RX_BRK_EOF_EN_R = crate::BitReader;
51#[doc = "Field `UART_RX_BRK_EOF_EN` writer - If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART."]
52pub type UART_RX_BRK_EOF_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
53impl R {
54 #[doc = "Bit 0 - Write 1, then write 0 to this bit to reset decode state machine."]
55 #[inline(always)]
56 pub fn tx_rst(&self) -> TX_RST_R {
57 TX_RST_R::new((self.bits & 1) != 0)
58 }
59 #[doc = "Bit 1 - Write 1, then write 0 to this bit to reset encode state machine."]
60 #[inline(always)]
61 pub fn rx_rst(&self) -> RX_RST_R {
62 RX_RST_R::new(((self.bits >> 1) & 1) != 0)
63 }
64 #[doc = "Bit 2 - Set this bit to link up HCI and UART0."]
65 #[inline(always)]
66 pub fn uart0_ce(&self) -> UART0_CE_R {
67 UART0_CE_R::new(((self.bits >> 2) & 1) != 0)
68 }
69 #[doc = "Bit 3 - Set this bit to link up HCI and UART1."]
70 #[inline(always)]
71 pub fn uart1_ce(&self) -> UART1_CE_R {
72 UART1_CE_R::new(((self.bits >> 3) & 1) != 0)
73 }
74 #[doc = "Bit 5 - Set this bit to separate the data frame using a special char."]
75 #[inline(always)]
76 pub fn seper_en(&self) -> SEPER_EN_R {
77 SEPER_EN_R::new(((self.bits >> 5) & 1) != 0)
78 }
79 #[doc = "Bit 6 - Set this bit to encode the data packet with a formatting header."]
80 #[inline(always)]
81 pub fn head_en(&self) -> HEAD_EN_R {
82 HEAD_EN_R::new(((self.bits >> 6) & 1) != 0)
83 }
84 #[doc = "Bit 7 - Set this bit to enable UHCI to receive the 16 bit CRC."]
85 #[inline(always)]
86 pub fn crc_rec_en(&self) -> CRC_REC_EN_R {
87 CRC_REC_EN_R::new(((self.bits >> 7) & 1) != 0)
88 }
89 #[doc = "Bit 8 - If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state."]
90 #[inline(always)]
91 pub fn uart_idle_eof_en(&self) -> UART_IDLE_EOF_EN_R {
92 UART_IDLE_EOF_EN_R::new(((self.bits >> 8) & 1) != 0)
93 }
94 #[doc = "Bit 9 - If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received."]
95 #[inline(always)]
96 pub fn len_eof_en(&self) -> LEN_EOF_EN_R {
97 LEN_EOF_EN_R::new(((self.bits >> 9) & 1) != 0)
98 }
99 #[doc = "Bit 10 - Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload."]
100 #[inline(always)]
101 pub fn encode_crc_en(&self) -> ENCODE_CRC_EN_R {
102 ENCODE_CRC_EN_R::new(((self.bits >> 10) & 1) != 0)
103 }
104 #[doc = "Bit 11 - 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers."]
105 #[inline(always)]
106 pub fn clk_en(&self) -> CLK_EN_R {
107 CLK_EN_R::new(((self.bits >> 11) & 1) != 0)
108 }
109 #[doc = "Bit 12 - If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART."]
110 #[inline(always)]
111 pub fn uart_rx_brk_eof_en(&self) -> UART_RX_BRK_EOF_EN_R {
112 UART_RX_BRK_EOF_EN_R::new(((self.bits >> 12) & 1) != 0)
113 }
114}
115#[cfg(feature = "impl-register-debug")]
116impl core::fmt::Debug for R {
117 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
118 f.debug_struct("CONF0")
119 .field("tx_rst", &self.tx_rst())
120 .field("rx_rst", &self.rx_rst())
121 .field("uart0_ce", &self.uart0_ce())
122 .field("uart1_ce", &self.uart1_ce())
123 .field("seper_en", &self.seper_en())
124 .field("head_en", &self.head_en())
125 .field("crc_rec_en", &self.crc_rec_en())
126 .field("uart_idle_eof_en", &self.uart_idle_eof_en())
127 .field("len_eof_en", &self.len_eof_en())
128 .field("encode_crc_en", &self.encode_crc_en())
129 .field("clk_en", &self.clk_en())
130 .field("uart_rx_brk_eof_en", &self.uart_rx_brk_eof_en())
131 .finish()
132 }
133}
134impl W {
135 #[doc = "Bit 0 - Write 1, then write 0 to this bit to reset decode state machine."]
136 #[inline(always)]
137 pub fn tx_rst(&mut self) -> TX_RST_W<CONF0_SPEC> {
138 TX_RST_W::new(self, 0)
139 }
140 #[doc = "Bit 1 - Write 1, then write 0 to this bit to reset encode state machine."]
141 #[inline(always)]
142 pub fn rx_rst(&mut self) -> RX_RST_W<CONF0_SPEC> {
143 RX_RST_W::new(self, 1)
144 }
145 #[doc = "Bit 2 - Set this bit to link up HCI and UART0."]
146 #[inline(always)]
147 pub fn uart0_ce(&mut self) -> UART0_CE_W<CONF0_SPEC> {
148 UART0_CE_W::new(self, 2)
149 }
150 #[doc = "Bit 3 - Set this bit to link up HCI and UART1."]
151 #[inline(always)]
152 pub fn uart1_ce(&mut self) -> UART1_CE_W<CONF0_SPEC> {
153 UART1_CE_W::new(self, 3)
154 }
155 #[doc = "Bit 5 - Set this bit to separate the data frame using a special char."]
156 #[inline(always)]
157 pub fn seper_en(&mut self) -> SEPER_EN_W<CONF0_SPEC> {
158 SEPER_EN_W::new(self, 5)
159 }
160 #[doc = "Bit 6 - Set this bit to encode the data packet with a formatting header."]
161 #[inline(always)]
162 pub fn head_en(&mut self) -> HEAD_EN_W<CONF0_SPEC> {
163 HEAD_EN_W::new(self, 6)
164 }
165 #[doc = "Bit 7 - Set this bit to enable UHCI to receive the 16 bit CRC."]
166 #[inline(always)]
167 pub fn crc_rec_en(&mut self) -> CRC_REC_EN_W<CONF0_SPEC> {
168 CRC_REC_EN_W::new(self, 7)
169 }
170 #[doc = "Bit 8 - If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state."]
171 #[inline(always)]
172 pub fn uart_idle_eof_en(&mut self) -> UART_IDLE_EOF_EN_W<CONF0_SPEC> {
173 UART_IDLE_EOF_EN_W::new(self, 8)
174 }
175 #[doc = "Bit 9 - If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received."]
176 #[inline(always)]
177 pub fn len_eof_en(&mut self) -> LEN_EOF_EN_W<CONF0_SPEC> {
178 LEN_EOF_EN_W::new(self, 9)
179 }
180 #[doc = "Bit 10 - Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload."]
181 #[inline(always)]
182 pub fn encode_crc_en(&mut self) -> ENCODE_CRC_EN_W<CONF0_SPEC> {
183 ENCODE_CRC_EN_W::new(self, 10)
184 }
185 #[doc = "Bit 11 - 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers."]
186 #[inline(always)]
187 pub fn clk_en(&mut self) -> CLK_EN_W<CONF0_SPEC> {
188 CLK_EN_W::new(self, 11)
189 }
190 #[doc = "Bit 12 - If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART."]
191 #[inline(always)]
192 pub fn uart_rx_brk_eof_en(&mut self) -> UART_RX_BRK_EOF_EN_W<CONF0_SPEC> {
193 UART_RX_BRK_EOF_EN_W::new(self, 12)
194 }
195}
196#[doc = "a\n\nYou can [`read`](crate::Reg::read) this register and get [`conf0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
197pub struct CONF0_SPEC;
198impl crate::RegisterSpec for CONF0_SPEC {
199 type Ux = u32;
200}
201#[doc = "`read()` method returns [`conf0::R`](R) reader structure"]
202impl crate::Readable for CONF0_SPEC {}
203#[doc = "`write(|w| ..)` method takes [`conf0::W`](W) writer structure"]
204impl crate::Writable for CONF0_SPEC {
205 type Safety = crate::Unsafe;
206}
207#[doc = "`reset()` method sets CONF0 to value 0x06e0"]
208impl crate::Resettable for CONF0_SPEC {
209 const RESET_VALUE: u32 = 0x06e0;
210}