esp32c3/spi1/
int_clr.rs

1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `PER_END` writer - The clear bit for SPI_MEM_PER_END_INT interrupt."]
4pub type PER_END_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `PES_END` writer - The clear bit for SPI_MEM_PES_END_INT interrupt."]
6pub type PES_END_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `WPE_END` writer - The clear bit for SPI_MEM_WPE_END_INT interrupt."]
8pub type WPE_END_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `SLV_ST_END` writer - The clear bit for SPI_MEM_SLV_ST_END_INT interrupt."]
10pub type SLV_ST_END_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `MST_ST_END` writer - The clear bit for SPI_MEM_MST_ST_END_INT interrupt."]
12pub type MST_ST_END_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[cfg(feature = "impl-register-debug")]
14impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
15    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
16        write!(f, "(not readable)")
17    }
18}
19impl W {
20    #[doc = "Bit 0 - The clear bit for SPI_MEM_PER_END_INT interrupt."]
21    #[inline(always)]
22    pub fn per_end(&mut self) -> PER_END_W<INT_CLR_SPEC> {
23        PER_END_W::new(self, 0)
24    }
25    #[doc = "Bit 1 - The clear bit for SPI_MEM_PES_END_INT interrupt."]
26    #[inline(always)]
27    pub fn pes_end(&mut self) -> PES_END_W<INT_CLR_SPEC> {
28        PES_END_W::new(self, 1)
29    }
30    #[doc = "Bit 2 - The clear bit for SPI_MEM_WPE_END_INT interrupt."]
31    #[inline(always)]
32    pub fn wpe_end(&mut self) -> WPE_END_W<INT_CLR_SPEC> {
33        WPE_END_W::new(self, 2)
34    }
35    #[doc = "Bit 3 - The clear bit for SPI_MEM_SLV_ST_END_INT interrupt."]
36    #[inline(always)]
37    pub fn slv_st_end(&mut self) -> SLV_ST_END_W<INT_CLR_SPEC> {
38        SLV_ST_END_W::new(self, 3)
39    }
40    #[doc = "Bit 4 - The clear bit for SPI_MEM_MST_ST_END_INT interrupt."]
41    #[inline(always)]
42    pub fn mst_st_end(&mut self) -> MST_ST_END_W<INT_CLR_SPEC> {
43        MST_ST_END_W::new(self, 4)
44    }
45}
46#[doc = "SPI1 interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
47pub struct INT_CLR_SPEC;
48impl crate::RegisterSpec for INT_CLR_SPEC {
49    type Ux = u32;
50}
51#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
52impl crate::Writable for INT_CLR_SPEC {
53    type Safety = crate::Unsafe;
54    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x1f;
55}
56#[doc = "`reset()` method sets INT_CLR to value 0"]
57impl crate::Resettable for INT_CLR_SPEC {}
esp32c3/spi1/int_clr.rs

esp32c3/spi1/
int_clr.rs
